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Commit 9acdc00c authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu/sdma4: add sdma4_0_1 support for vega12 (v3) 



Add sdma golden setting for vega12.

v2: switch to soc15_program_register_sequence for
golden register programming
v3: squash in unused declaration fix

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 900bad3f

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+15 −3
Original line number Diff line number Diff line
@@ -86,6 +86,13 @@ static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 
	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)

};



static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),

	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)

};



static const struct soc15_reg_golden golden_settings_sdma_4_1[] =

{

	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
@@ -125,7 +132,12 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 
						 ARRAY_SIZE(golden_settings_sdma_vg10));

		break;

	case CHIP_VEGA12:

		DRM_ERROR("todo: Missing SDMA4 golden settings for vega12\n");

		soc15_program_register_sequence(adev,

						golden_settings_sdma_4,

						ARRAY_SIZE(golden_settings_sdma_4));

		soc15_program_register_sequence(adev,

						golden_settings_sdma_vg12,

						ARRAY_SIZE(golden_settings_sdma_vg12));

		break;

	case CHIP_RAVEN:

		soc15_program_register_sequence(adev,
@@ -1627,7 +1639,7 @@ static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 
 * @dst_offset: dst GPU address

 * @byte_count: number of bytes to xfer

 *

 * Copy GPU buffers using the DMA engine (VEGA10).

 * Copy GPU buffers using the DMA engine (VEGA10/12).

 * Used by the amdgpu ttm implementation to move pages if

 * registered as the asic copy callback.

 */
@@ -1654,7 +1666,7 @@ static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 
 * @dst_offset: dst GPU address

 * @byte_count: number of bytes to xfer

 *

 * Fill GPU buffers using the DMA engine (VEGA10).

 * Fill GPU buffers using the DMA engine (VEGA10/12).

 */

static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,

				       uint32_t src_data,