ARM: pgtable: document mapping types

/*

 * These are the memory types, defined to be compatible with

 * pre-ARMv6 CPUs cacheable and bufferable bits:   XXCB

 * pre-ARMv6 CPUs cacheable and bufferable bits: n/a,n/a,C,B

 * ARMv6+ without TEX remapping, they are a table index.

 * ARMv6+ with TEX remapping, they correspond to n/a,TEX(0),C,B

 *

 * MT type		Pre-ARMv6	ARMv6+ type / cacheable status

 * UNCACHED		Uncached	Strongly ordered

 * BUFFERABLE		Bufferable	Normal memory / non-cacheable

 * WRITETHROUGH		Writethrough	Normal memory / write through

 * WRITEBACK		Writeback	Normal memory / write back, read alloc

 * MINICACHE		Minicache	N/A

 * WRITEALLOC		Writeback	Normal memory / write back, write alloc

 * DEV_SHARED		Uncached	Device memory (shared)

 * DEV_NONSHARED	Uncached	Device memory (non-shared)

 * DEV_WC		Bufferable	Normal memory / non-cacheable

 * DEV_CACHED		Writeback	Normal memory / write back, read alloc

 * VECTORS		Variable	Normal memory / variable

 *

 * All normal memory mappings have the following properties:

 * - reads can be repeated with no side effects

 * - repeated reads return the last value written

 * - reads can fetch additional locations without side effects

 * - writes can be repeated (in certain cases) with no side effects

 * - writes can be merged before accessing the target

 * - unaligned accesses can be supported

 *

 * All device mappings have the following properties:

 * - no access speculation

 * - no repetition (eg, on return from an exception)

 * - number, order and size of accesses are maintained

 * - unaligned accesses are "unpredictable"

 */

#define L_PTE_MT_UNCACHED	(_AT(pteval_t, 0x00) << 2)	/* 0000 */

#define L_PTE_MT_BUFFERABLE	(_AT(pteval_t, 0x01) << 2)	/* 0001 */