Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9a45d33c authored by Boris Brezillon's avatar Boris Brezillon
Browse files

drm/atmel-hlcdc: Simplify the HLCDC layer logic 



An HLCDC layers in Atmel's nomenclature is either a DRM plane or a 'Post
Processing Layer' which can be used to output the results of the HLCDC
composition in a memory buffer.

atmel_hlcdc_layer.c was designed to be generic enough to be re-usable in
both cases, but we're not exposing the post-processing layer yet, and
even if we were, I'm not sure the code would provide the necessary tools
to manipulate this kind of layer.

Moreover, the code in atmel_hlcdc_{plane,layer}.c was designed before the
atomic modesetting API, and was trying solve the
check-setting/commit-if-ok/rollback-otherwise problem, which is now
entirely solved by the existing core infrastructure.

And finally, the code in atmel_hlcdc_layer.c is over-complicated compared
to what we really need. This rework is a good excuse to simplify it. Note
that this rework solves an existing resource leak (leading to a -EBUSY
error) which I failed to clearly identify.

Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: default avatarEric Anholt <eric@anholt.net>
Tested-by: default avatarNicolas Ferre <nicolas.ferre@microchip.com>
parent 6140cf20

drivers/gpu/drm/atmel-hlcdc/Makefile

+0 −1
Original line number Diff line number Diff line 
atmel-hlcdc-dc-y := atmel_hlcdc_crtc.o \

		atmel_hlcdc_dc.o \

		atmel_hlcdc_layer.o \

		atmel_hlcdc_output.o \

		atmel_hlcdc_plane.o

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c

+30 −9
Original line number Diff line number Diff line
@@ -466,8 +466,8 @@ static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = { 


int atmel_hlcdc_crtc_create(struct drm_device *dev)

{

	struct atmel_hlcdc_plane *primary = NULL, *cursor = NULL;

	struct atmel_hlcdc_dc *dc = dev->dev_private;

	struct atmel_hlcdc_planes *planes = dc->planes;

	struct atmel_hlcdc_crtc *crtc;

	int ret;

	int i;
@@ -478,20 +478,41 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev) 


	crtc->dc = dc;



	ret = drm_crtc_init_with_planes(dev, &crtc->base,

				&planes->primary->base,

				planes->cursor ? &planes->cursor->base : NULL,

				&atmel_hlcdc_crtc_funcs, NULL);

	for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {

		if (!dc->layers[i])

			continue;



		switch (dc->layers[i]->desc->type) {

		case ATMEL_HLCDC_BASE_LAYER:

			primary = atmel_hlcdc_layer_to_plane(dc->layers[i]);

			break;



		case ATMEL_HLCDC_CURSOR_LAYER:

			cursor = atmel_hlcdc_layer_to_plane(dc->layers[i]);

			break;



		default:

			break;

		}

	}



	ret = drm_crtc_init_with_planes(dev, &crtc->base, &primary->base,

					&cursor->base, &atmel_hlcdc_crtc_funcs,

					NULL);

	if (ret < 0)

		goto fail;



	crtc->id = drm_crtc_index(&crtc->base);



	if (planes->cursor)

		planes->cursor->base.possible_crtcs = 1 << crtc->id;

	for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {

		struct atmel_hlcdc_plane *overlay;



	for (i = 0; i < planes->noverlays; i++)

		planes->overlays[i]->base.possible_crtcs = 1 << crtc->id;

		if (dc->layers[i] &&

		    dc->layers[i]->desc->type == ATMEL_HLCDC_OVERLAY_LAYER) {

			overlay = atmel_hlcdc_layer_to_plane(dc->layers[i]);

			overlay->base.possible_crtcs = 1 << crtc->id;

		}

	}



	drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs);

	drm_crtc_vblank_reset(&crtc->base);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c

+43 −39
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = { 
		.regs_offset = 0x40,

		.id = 0,

		.type = ATMEL_HLCDC_BASE_LAYER,

		.nconfigs = 5,

		.cfgs_offset = 0x2c,

		.layout = {

			.xstride = { 2 },

			.default_color = 3,
@@ -65,7 +65,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = { 
		.regs_offset = 0x40,

		.id = 0,

		.type = ATMEL_HLCDC_BASE_LAYER,

		.nconfigs = 5,

		.cfgs_offset = 0x2c,

		.layout = {

			.xstride = { 2 },

			.default_color = 3,
@@ -80,7 +80,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = { 
		.regs_offset = 0x100,

		.id = 1,

		.type = ATMEL_HLCDC_OVERLAY_LAYER,

		.nconfigs = 10,

		.cfgs_offset = 0x2c,

		.layout = {

			.pos = 2,

			.size = 3,
@@ -98,7 +98,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = { 
		.regs_offset = 0x280,

		.id = 2,

		.type = ATMEL_HLCDC_OVERLAY_LAYER,

		.nconfigs = 17,

		.cfgs_offset = 0x4c,

		.layout = {

			.pos = 2,

			.size = 3,
@@ -109,6 +109,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = { 
			.chroma_key = 10,

			.chroma_key_mask = 11,

			.general_config = 12,

			.scaler_config = 13,

			.csc = 14,

		},

	},
@@ -118,9 +119,9 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = { 
		.regs_offset = 0x340,

		.id = 3,

		.type = ATMEL_HLCDC_CURSOR_LAYER,

		.nconfigs = 10,

		.max_width = 128,

		.max_height = 128,

		.cfgs_offset = 0x2c,

		.layout = {

			.pos = 2,

			.size = 3,
@@ -153,7 +154,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = { 
		.regs_offset = 0x40,

		.id = 0,

		.type = ATMEL_HLCDC_BASE_LAYER,

		.nconfigs = 7,

		.cfgs_offset = 0x2c,

		.layout = {

			.xstride = { 2 },

			.default_color = 3,
@@ -168,7 +169,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = { 
		.regs_offset = 0x140,

		.id = 1,

		.type = ATMEL_HLCDC_OVERLAY_LAYER,

		.nconfigs = 10,

		.cfgs_offset = 0x2c,

		.layout = {

			.pos = 2,

			.size = 3,
@@ -186,7 +187,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = { 
		.regs_offset = 0x240,

		.id = 2,

		.type = ATMEL_HLCDC_OVERLAY_LAYER,

		.nconfigs = 10,

		.cfgs_offset = 0x2c,

		.layout = {

			.pos = 2,

			.size = 3,
@@ -204,7 +205,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = { 
		.regs_offset = 0x340,

		.id = 3,

		.type = ATMEL_HLCDC_OVERLAY_LAYER,

		.nconfigs = 42,

		.cfgs_offset = 0x4c,

		.layout = {

			.pos = 2,

			.size = 3,
@@ -215,6 +216,11 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = { 
			.chroma_key = 10,

			.chroma_key_mask = 11,

			.general_config = 12,

			.scaler_config = 13,

			.phicoeffs = {

				.x = 17,

				.y = 33,

			},

			.csc = 14,

		},

	},
@@ -224,9 +230,9 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = { 
		.regs_offset = 0x440,

		.id = 4,

		.type = ATMEL_HLCDC_CURSOR_LAYER,

		.nconfigs = 10,

		.max_width = 128,

		.max_height = 128,

		.cfgs_offset = 0x2c,

		.layout = {

			.pos = 2,

			.size = 3,
@@ -236,6 +242,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = { 
			.chroma_key = 7,

			.chroma_key_mask = 8,

			.general_config = 9,

			.scaler_config = 13,

		},

	},

};
@@ -260,7 +267,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = { 
		.regs_offset = 0x40,

		.id = 0,

		.type = ATMEL_HLCDC_BASE_LAYER,

		.nconfigs = 7,

		.cfgs_offset = 0x2c,

		.layout = {

			.xstride = { 2 },

			.default_color = 3,
@@ -275,7 +282,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = { 
		.regs_offset = 0x140,

		.id = 1,

		.type = ATMEL_HLCDC_OVERLAY_LAYER,

		.nconfigs = 10,

		.cfgs_offset = 0x2c,

		.layout = {

			.pos = 2,

			.size = 3,
@@ -293,7 +300,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = { 
		.regs_offset = 0x240,

		.id = 2,

		.type = ATMEL_HLCDC_OVERLAY_LAYER,

		.nconfigs = 10,

		.cfgs_offset = 0x2c,

		.layout = {

			.pos = 2,

			.size = 3,
@@ -311,7 +318,7 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = { 
		.regs_offset = 0x340,

		.id = 3,

		.type = ATMEL_HLCDC_OVERLAY_LAYER,

		.nconfigs = 42,

		.cfgs_offset = 0x4c,

		.layout = {

			.pos = 2,

			.size = 3,
@@ -322,6 +329,11 @@ static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = { 
			.chroma_key = 10,

			.chroma_key_mask = 11,

			.general_config = 12,

			.scaler_config = 13,

			.phicoeffs = {

				.x = 17,

				.y = 33,

			},

			.csc = 14,

		},

	},
@@ -392,6 +404,17 @@ int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc, 
	return MODE_OK;

}



static void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer)

{

	if (!layer)

		return;



	if (layer->desc->type == ATMEL_HLCDC_BASE_LAYER ||

	    layer->desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||

	    layer->desc->type == ATMEL_HLCDC_CURSOR_LAYER)

		atmel_hlcdc_plane_irq(atmel_hlcdc_layer_to_plane(layer));

}



static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)

{

	struct drm_device *dev = data;
@@ -410,12 +433,8 @@ static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data) 
		atmel_hlcdc_crtc_irq(dc->crtc);



	for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {

		struct atmel_hlcdc_layer *layer = dc->layers[i];



		if (!(ATMEL_HLCDC_LAYER_STATUS(i) & status) || !layer)

			continue;



		atmel_hlcdc_layer_irq(layer);

		if (ATMEL_HLCDC_LAYER_STATUS(i) & status)

			atmel_hlcdc_layer_irq(dc->layers[i]);

	}



	return IRQ_HANDLED;
@@ -537,9 +556,7 @@ static const struct drm_mode_config_funcs mode_config_funcs = { 
static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)

{

	struct atmel_hlcdc_dc *dc = dev->dev_private;

	struct atmel_hlcdc_planes *planes;

	int ret;

	int i;



	drm_mode_config_init(dev);
@@ -549,25 +566,12 @@ static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev) 
		return ret;

	}



	planes = atmel_hlcdc_create_planes(dev);

	if (IS_ERR(planes)) {

		dev_err(dev->dev, "failed to create planes\n");

		return PTR_ERR(planes);

	ret = atmel_hlcdc_create_planes(dev);

	if (ret) {

		dev_err(dev->dev, "failed to create planes: %d\n", ret);

		return ret;

	}



	dc->planes = planes;



	dc->layers[planes->primary->layer.desc->id] =

						&planes->primary->layer;



	if (planes->cursor)

		dc->layers[planes->cursor->layer.desc->id] =

							&planes->cursor->layer;



	for (i = 0; i < planes->noverlays; i++)

		dc->layers[planes->overlays[i]->layer.desc->id] =

						&planes->overlays[i]->layer;



	ret = atmel_hlcdc_crtc_create(dev);

	if (ret) {

		dev_err(dev->dev, "failed to create crtc\n");

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h

+311 −50
Original line number Diff line number Diff line
@@ -23,7 +23,9 @@ 
#define DRM_ATMEL_HLCDC_H



#include <linux/clk.h>

#include <linux/dmapool.h>

#include <linux/irqdomain.h>

#include <linux/mfd/atmel-hlcdc.h>

#include <linux/pwm.h>



#include <drm/drm_atomic.h>
@@ -36,51 +38,245 @@ 
#include <drm/drm_plane_helper.h>

#include <drm/drmP.h>



#include "atmel_hlcdc_layer.h"

#define ATMEL_HLCDC_LAYER_CHER			0x0

#define ATMEL_HLCDC_LAYER_CHDR			0x4

#define ATMEL_HLCDC_LAYER_CHSR			0x8

#define ATMEL_HLCDC_LAYER_EN			BIT(0)

#define ATMEL_HLCDC_LAYER_UPDATE		BIT(1)

#define ATMEL_HLCDC_LAYER_A2Q			BIT(2)

#define ATMEL_HLCDC_LAYER_RST			BIT(8)



#define ATMEL_HLCDC_MAX_LAYERS		5

#define ATMEL_HLCDC_LAYER_IER			0xc

#define ATMEL_HLCDC_LAYER_IDR			0x10

#define ATMEL_HLCDC_LAYER_IMR			0x14

#define ATMEL_HLCDC_LAYER_ISR			0x18

#define ATMEL_HLCDC_LAYER_DFETCH		BIT(0)

#define ATMEL_HLCDC_LAYER_LFETCH		BIT(1)

#define ATMEL_HLCDC_LAYER_DMA_IRQ(p)		BIT(2 + (8 * (p)))

#define ATMEL_HLCDC_LAYER_DSCR_IRQ(p)		BIT(3 + (8 * (p)))

#define ATMEL_HLCDC_LAYER_ADD_IRQ(p)		BIT(4 + (8 * (p)))

#define ATMEL_HLCDC_LAYER_DONE_IRQ(p)		BIT(5 + (8 * (p)))

#define ATMEL_HLCDC_LAYER_OVR_IRQ(p)		BIT(6 + (8 * (p)))



#define ATMEL_HLCDC_LAYER_PLANE_HEAD(p)		(((p) * 0x10) + 0x1c)

#define ATMEL_HLCDC_LAYER_PLANE_ADDR(p)		(((p) * 0x10) + 0x20)

#define ATMEL_HLCDC_LAYER_PLANE_CTRL(p)		(((p) * 0x10) + 0x24)

#define ATMEL_HLCDC_LAYER_PLANE_NEXT(p)		(((p) * 0x10) + 0x28)



#define ATMEL_HLCDC_LAYER_DMA_CFG		0

#define ATMEL_HLCDC_LAYER_DMA_SIF		BIT(0)

#define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK		GENMASK(5, 4)

#define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE	(0 << 4)

#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4	(1 << 4)

#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8	(2 << 4)

#define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16	(3 << 4)

#define ATMEL_HLCDC_LAYER_DMA_DLBO		BIT(8)

#define ATMEL_HLCDC_LAYER_DMA_ROTDIS		BIT(12)

#define ATMEL_HLCDC_LAYER_DMA_LOCKDIS		BIT(13)



#define ATMEL_HLCDC_LAYER_FORMAT_CFG		1

#define ATMEL_HLCDC_LAYER_RGB			(0 << 0)

#define ATMEL_HLCDC_LAYER_CLUT			(1 << 0)

#define ATMEL_HLCDC_LAYER_YUV			(2 << 0)

#define ATMEL_HLCDC_RGB_MODE(m)			\

	(ATMEL_HLCDC_LAYER_RGB | (((m) & 0xf) << 4))

#define ATMEL_HLCDC_CLUT_MODE(m)		\

	(ATMEL_HLCDC_LAYER_CLUT | (((m) & 0x3) << 8))

#define ATMEL_HLCDC_YUV_MODE(m)			\

	(ATMEL_HLCDC_LAYER_YUV | (((m) & 0xf) << 12))

#define ATMEL_HLCDC_YUV422ROT			BIT(16)

#define ATMEL_HLCDC_YUV422SWP			BIT(17)

#define ATMEL_HLCDC_DSCALEOPT			BIT(20)



#define ATMEL_HLCDC_XRGB4444_MODE		ATMEL_HLCDC_RGB_MODE(0)

#define ATMEL_HLCDC_ARGB4444_MODE		ATMEL_HLCDC_RGB_MODE(1)

#define ATMEL_HLCDC_RGBA4444_MODE		ATMEL_HLCDC_RGB_MODE(2)

#define ATMEL_HLCDC_RGB565_MODE			ATMEL_HLCDC_RGB_MODE(3)

#define ATMEL_HLCDC_ARGB1555_MODE		ATMEL_HLCDC_RGB_MODE(4)

#define ATMEL_HLCDC_XRGB8888_MODE		ATMEL_HLCDC_RGB_MODE(9)

#define ATMEL_HLCDC_RGB888_MODE			ATMEL_HLCDC_RGB_MODE(10)

#define ATMEL_HLCDC_ARGB8888_MODE		ATMEL_HLCDC_RGB_MODE(12)

#define ATMEL_HLCDC_RGBA8888_MODE		ATMEL_HLCDC_RGB_MODE(13)



#define ATMEL_HLCDC_AYUV_MODE			ATMEL_HLCDC_YUV_MODE(0)

#define ATMEL_HLCDC_YUYV_MODE			ATMEL_HLCDC_YUV_MODE(1)

#define ATMEL_HLCDC_UYVY_MODE			ATMEL_HLCDC_YUV_MODE(2)

#define ATMEL_HLCDC_YVYU_MODE			ATMEL_HLCDC_YUV_MODE(3)

#define ATMEL_HLCDC_VYUY_MODE			ATMEL_HLCDC_YUV_MODE(4)

#define ATMEL_HLCDC_NV61_MODE			ATMEL_HLCDC_YUV_MODE(5)

#define ATMEL_HLCDC_YUV422_MODE			ATMEL_HLCDC_YUV_MODE(6)

#define ATMEL_HLCDC_NV21_MODE			ATMEL_HLCDC_YUV_MODE(7)

#define ATMEL_HLCDC_YUV420_MODE			ATMEL_HLCDC_YUV_MODE(8)



#define ATMEL_HLCDC_LAYER_POS(x, y)		((x) | ((y) << 16))

#define ATMEL_HLCDC_LAYER_SIZE(w, h)		(((w) - 1) | (((h) - 1) << 16))



#define ATMEL_HLCDC_LAYER_CRKEY			BIT(0)

#define ATMEL_HLCDC_LAYER_INV			BIT(1)

#define ATMEL_HLCDC_LAYER_ITER2BL		BIT(2)

#define ATMEL_HLCDC_LAYER_ITER			BIT(3)

#define ATMEL_HLCDC_LAYER_REVALPHA		BIT(4)

#define ATMEL_HLCDC_LAYER_GAEN			BIT(5)

#define ATMEL_HLCDC_LAYER_LAEN			BIT(6)

#define ATMEL_HLCDC_LAYER_OVR			BIT(7)

#define ATMEL_HLCDC_LAYER_DMA			BIT(8)

#define ATMEL_HLCDC_LAYER_REP			BIT(9)

#define ATMEL_HLCDC_LAYER_DSTKEY		BIT(10)

#define ATMEL_HLCDC_LAYER_DISCEN		BIT(11)

#define ATMEL_HLCDC_LAYER_GA_SHIFT		16

#define ATMEL_HLCDC_LAYER_GA_MASK		\

	GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT)

#define ATMEL_HLCDC_LAYER_GA(x)			\

	((x) << ATMEL_HLCDC_LAYER_GA_SHIFT)



#define ATMEL_HLCDC_LAYER_DISC_POS(x, y)	((x) | ((y) << 16))

#define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h)	(((w) - 1) | (((h) - 1) << 16))



#define ATMEL_HLCDC_LAYER_SCALER_FACTORS(x, y)	((x) | ((y) << 16))

#define ATMEL_HLCDC_LAYER_SCALER_ENABLE		BIT(31)



#define ATMEL_HLCDC_LAYER_MAX_PLANES		3



#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED	BIT(0)

#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED	BIT(1)

#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE	BIT(2)

#define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN	BIT(3)



#define ATMEL_HLCDC_MAX_LAYERS			6



/**

 * Atmel HLCDC Display Controller description structure.

 * Atmel HLCDC Layer registers layout structure

 *

 * This structure describe the HLCDC IP capabilities and depends on the

 * HLCDC IP version (or Atmel SoC family).

 * Each HLCDC layer has its own register organization and a given register

 * can be placed differently on 2 different layers depending on its

 * capabilities.

 * This structure stores common registers layout for a given layer and is

 * used by HLCDC layer code to choose the appropriate register to write to

 * or to read from.

 *

 * @min_width: minimum width supported by the Display Controller

 * @min_height: minimum height supported by the Display Controller

 * @max_width: maximum width supported by the Display Controller

 * @max_height: maximum height supported by the Display Controller

 * @max_spw: maximum vertical/horizontal pulse width

 * @max_vpw: maximum vertical back/front porch width

 * @max_hpw: maximum horizontal back/front porch width

 * @conflicting_output_formats: true if RGBXXX output formats conflict with

 *				each other.

 * @layers: a layer description table describing available layers

 * @nlayers: layer description table size

 * For all fields, a value of zero means "unsupported".

 *

 * See Atmel's datasheet for a detailled description of these registers.

 *

 * @xstride: xstride registers

 * @pstride: pstride registers

 * @pos: position register

 * @size: displayed size register

 * @memsize: memory size register

 * @default_color: default color register

 * @chroma_key: chroma key register

 * @chroma_key_mask: chroma key mask register

 * @general_config: general layer config register

 * @sacler_config: scaler factors register

 * @phicoeffs: X/Y PHI coefficient registers

 * @disc_pos: discard area position register

 * @disc_size: discard area size register

 * @csc: color space conversion register

 */

struct atmel_hlcdc_dc_desc {

	int min_width;

	int min_height;

struct atmel_hlcdc_layer_cfg_layout {

	int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES];

	int pstride[ATMEL_HLCDC_LAYER_MAX_PLANES];

	int pos;

	int size;

	int memsize;

	int default_color;

	int chroma_key;

	int chroma_key_mask;

	int general_config;

	int scaler_config;

	struct {

		int x;

		int y;

	} phicoeffs;

	int disc_pos;

	int disc_size;

	int csc;

};



/**

 * Atmel HLCDC DMA descriptor structure

 *

 * This structure is used by the HLCDC DMA engine to schedule a DMA transfer.

 *

 * The structure fields must remain in this specific order, because they're

 * used by the HLCDC DMA engine, which expect them in this order.

 * HLCDC DMA descriptors must be aligned on 64 bits.

 *

 * @addr: buffer DMA address

 * @ctrl: DMA transfer options

 * @next: next DMA descriptor to fetch

 * @self: descriptor DMA address

 */

struct atmel_hlcdc_dma_channel_dscr {

	dma_addr_t addr;

	u32 ctrl;

	dma_addr_t next;

	dma_addr_t self;

} __aligned(sizeof(u64));



/**

 * Atmel HLCDC layer types

 */

enum atmel_hlcdc_layer_type {

	ATMEL_HLCDC_NO_LAYER,

	ATMEL_HLCDC_BASE_LAYER,

	ATMEL_HLCDC_OVERLAY_LAYER,

	ATMEL_HLCDC_CURSOR_LAYER,

	ATMEL_HLCDC_PP_LAYER,

};



/**

 * Atmel HLCDC Supported formats structure

 *

 * This structure list all the formats supported by a given layer.

 *

 * @nformats: number of supported formats

 * @formats: supported formats

 */

struct atmel_hlcdc_formats {

	int nformats;

	u32 *formats;

};



/**

 * Atmel HLCDC Layer description structure

 *

 * This structure describes the capabilities provided by a given layer.

 *

 * @name: layer name

 * @type: layer type

 * @id: layer id

 * @regs_offset: offset of the layer registers from the HLCDC registers base

 * @cfgs_offset: CFGX registers offset from the layer registers base

 * @formats: supported formats

 * @layout: config registers layout

 * @max_width: maximum width supported by this layer (0 means unlimited)

 * @max_height: maximum height supported by this layer (0 means unlimited)

 */

struct atmel_hlcdc_layer_desc {

	const char *name;

	enum atmel_hlcdc_layer_type type;

	int id;

	int regs_offset;

	int cfgs_offset;

	struct atmel_hlcdc_formats *formats;

	struct atmel_hlcdc_layer_cfg_layout layout;

	int max_width;

	int max_height;

	int max_spw;

	int max_vpw;

	int max_hpw;

	bool conflicting_output_formats;

	const struct atmel_hlcdc_layer_desc *layers;

	int nlayers;

};



/**

 * Atmel HLCDC Plane properties.

 * Atmel HLCDC Layer.

 *

 * This structure stores plane property definitions.

 * A layer can be a DRM plane of a post processing layer used to render

 * HLCDC composition into memory.

 *

 * @alpha: alpha blending (or transparency) property

 * @rotation: rotation property

 * @desc: layer description

 * @regmap: pointer to the HLCDC regmap

 */

struct atmel_hlcdc_plane_properties {

	struct drm_property *alpha;

struct atmel_hlcdc_layer {

	const struct atmel_hlcdc_layer_desc *desc;

	struct regmap *regmap;

};



/**
@@ -89,7 +285,6 @@ struct atmel_hlcdc_plane_properties { 
 * @base: base DRM plane structure

 * @layer: HLCDC layer structure

 * @properties: pointer to the property definitions structure

 * @rotation: current rotation status

 */

struct atmel_hlcdc_plane {

	struct drm_plane base;
@@ -104,47 +299,73 @@ drm_plane_to_atmel_hlcdc_plane(struct drm_plane *p) 
}



static inline struct atmel_hlcdc_plane *

atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *l)

atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer)

{

	return container_of(l, struct atmel_hlcdc_plane, layer);

	return container_of(layer, struct atmel_hlcdc_plane, layer);

}



/**

 * Atmel HLCDC Planes.

 * Atmel HLCDC Display Controller description structure.

 *

 * This structure stores the instantiated HLCDC Planes and can be accessed by

 * the HLCDC Display Controller or the HLCDC CRTC.

 * This structure describes the HLCDC IP capabilities and depends on the

 * HLCDC IP version (or Atmel SoC family).

 *

 * @primary: primary plane

 * @cursor: hardware cursor plane

 * @overlays: overlay plane table

 * @noverlays: number of overlay planes

 * @min_width: minimum width supported by the Display Controller

 * @min_height: minimum height supported by the Display Controller

 * @max_width: maximum width supported by the Display Controller

 * @max_height: maximum height supported by the Display Controller

 * @max_spw: maximum vertical/horizontal pulse width

 * @max_vpw: maximum vertical back/front porch width

 * @max_hpw: maximum horizontal back/front porch width

 * @conflicting_output_formats: true if RGBXXX output formats conflict with

 *				each other.

 * @layers: a layer description table describing available layers

 * @nlayers: layer description table size

 */

struct atmel_hlcdc_planes {

	struct atmel_hlcdc_plane *primary;

	struct atmel_hlcdc_plane *cursor;

	struct atmel_hlcdc_plane **overlays;

	int noverlays;

struct atmel_hlcdc_dc_desc {

	int min_width;

	int min_height;

	int max_width;

	int max_height;

	int max_spw;

	int max_vpw;

	int max_hpw;

	bool conflicting_output_formats;

	const struct atmel_hlcdc_layer_desc *layers;

	int nlayers;

};



/**

 * Atmel HLCDC Plane properties.

 *

 * This structure stores plane property definitions.

 *

 * @alpha: alpha blending (or transparency) property

 * @rotation: rotation property

 */

struct atmel_hlcdc_plane_properties {

	struct drm_property *alpha;

};



/**

 * Atmel HLCDC Display Controller.

 *

 * @desc: HLCDC Display Controller description

 * @dscrpool: DMA coherent pool used to allocate DMA descriptors

 * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device

 * @fbdev: framebuffer device attached to the Display Controller

 * @crtc: CRTC provided by the display controller

 * @planes: instantiated planes

 * @layers: active HLCDC layer

 * @layers: active HLCDC layers

 * @wq: display controller workqueue

 * @commit: used for async commit handling

 */

struct atmel_hlcdc_dc {

	const struct atmel_hlcdc_dc_desc *desc;

	struct dma_pool *dscrpool;

	struct atmel_hlcdc *hlcdc;

	struct drm_fbdev_cma *fbdev;

	struct drm_crtc *crtc;

	struct atmel_hlcdc_planes *planes;

	struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS];

	struct workqueue_struct *wq;

	struct {
@@ -156,11 +377,51 @@ struct atmel_hlcdc_dc { 
extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats;

extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats;



static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer,

					       unsigned int reg, u32 val)

{

	regmap_write(layer->regmap, layer->desc->regs_offset + reg, val);

}



static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer,

					     unsigned int reg)

{

	u32 val;



	regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val);



	return val;

}



static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer,

					       unsigned int cfgid, u32 val)

{

	atmel_hlcdc_layer_write_reg(layer,

				    layer->desc->cfgs_offset +

				    (cfgid * sizeof(u32)), val);

}



static inline u32 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer *layer,

					     unsigned int cfgid)

{

	return atmel_hlcdc_layer_read_reg(layer,

					  layer->desc->cfgs_offset +

					  (cfgid * sizeof(u32)));

}



static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer,

				const struct atmel_hlcdc_layer_desc *desc,

				struct regmap *regmap)

{

	layer->desc = desc;

	layer->regmap = regmap;

}



int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,

			      struct drm_display_mode *mode);



struct atmel_hlcdc_planes *

atmel_hlcdc_create_planes(struct drm_device *dev);

int atmel_hlcdc_create_planes(struct drm_device *dev);

void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane);



int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state);

int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state);

drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c

deleted100644 → 0
+0 −666

File deleted.

Preview size limit exceeded, changes collapsed.