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Unverified Commit 9a3a92cc authored May 14, 2018 by Maciej W. Rozycki Committed by James Hogan May 14, 2018

MIPS: Fix ptrace(2) PTRACE_PEEKUSR and PTRACE_POKEUSR accesses to o32 FGRs



Check the TIF_32BIT_FPREGS task setting of the tracee rather than the
tracer in determining the layout of floating-point general registers in
the floating-point context, correcting access to odd-numbered registers
for o32 tracees where the setting disagrees between the two processes.

Fixes: 597ce172 ("MIPS: Support for 64-bit FP with O32 binaries")
Signed-off-by: Maciej W. Rozycki <macro@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.14+
Signed-off-by: James Hogan <jhogan@kernel.org>

parent 947bc875

arch/mips/kernel/ptrace.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -807,7 +807,7 @@ long arch_ptrace(struct task_struct *child, long request,
		fregs = get_fpu_regs(child);

		#ifdef CONFIG_32BIT
		if (test_thread_flag(TIF_32BIT_FPREGS)) {
		if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
		/*
		* The odd registers are actually the high
		* order bits of the values stored in the even
		@@ -902,7 +902,7 @@ long arch_ptrace(struct task_struct *child, long request,

		init_fp_ctx(child);
		#ifdef CONFIG_32BIT
		if (test_thread_flag(TIF_32BIT_FPREGS)) {
		if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
		/*
		* The odd registers are actually the high
		* order bits of the values stored in the even

arch/mips/kernel/ptrace32.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -99,7 +99,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
		break;
		}
		fregs = get_fpu_regs(child);
		if (test_thread_flag(TIF_32BIT_FPREGS)) {
		if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
		/*
		* The odd registers are actually the high
		* order bits of the values stored in the even
		@@ -212,7 +212,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
		sizeof(child->thread.fpu));
		child->thread.fpu.fcr31 = 0;
		}
		if (test_thread_flag(TIF_32BIT_FPREGS)) {
		if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
		/*
		* The odd registers are actually the high
		* order bits of the values stored in the even