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Commit 99fe7e1d authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Poll a6x crashdumper register memory for status"

parents 843e94b9 46666ab8

drivers/gpu/msm/adreno_a6xx_snapshot.c

+40 −7
Original line number Diff line number Diff line
@@ -679,6 +679,7 @@ static struct a6xx_shader_block a615_shader_blocks[] = { 
static struct kgsl_memdesc a6xx_capturescript;

static struct kgsl_memdesc a6xx_crashdump_registers;

static bool crash_dump_valid;

static u32 *a6xx_cd_reg_end;



static struct reg_list {

	const unsigned int *regs;
@@ -1656,9 +1657,9 @@ static size_t a6xx_snapshot_sqe(struct kgsl_device *device, u8 *buf, 


static void _a6xx_do_crashdump(struct kgsl_device *device)

{

	unsigned long wait_time;

	unsigned int reg = 0;

	unsigned int val;

	ktime_t timeout;



	crash_dump_valid = false;
@@ -1685,14 +1686,25 @@ static void _a6xx_do_crashdump(struct kgsl_device *device) 
			upper_32_bits(a6xx_capturescript.gpuaddr));

	kgsl_regwrite(device, A6XX_CP_CRASH_DUMP_CNTL, 1);



	wait_time = jiffies + msecs_to_jiffies(CP_CRASH_DUMPER_TIMEOUT);

	while (!time_after(jiffies, wait_time)) {

		kgsl_regread(device, A6XX_CP_CRASH_DUMP_STATUS, &reg);

		if (reg & 0x2)

	timeout = ktime_add_ms(ktime_get(), CP_CRASH_DUMPER_TIMEOUT);



	might_sleep();



	for (;;) {

		/* make sure we're reading the latest value */

		rmb();

		if ((*a6xx_cd_reg_end) != 0xaaaaaaaa)

			break;



		if (ktime_compare(ktime_get(), timeout) > 0)

			break;

		cpu_relax();



		/* Wait 1msec to avoid unnecessary looping */

		usleep_range(100, 1000);

	}



	kgsl_regread(device, A6XX_CP_CRASH_DUMP_STATUS, &reg);



	if (!ADRENO_FEATURE(ADRENO_DEVICE(device), ADRENO_APRIV))

		kgsl_regwrite(device, A6XX_CP_MISC_CNTL, 0);
@@ -1830,7 +1842,7 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, 
	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	struct adreno_ringbuffer *rb;

	bool sptprac_on;

	unsigned int i, roq_size, ucode_dbg_size;

	unsigned int i, roq_size, ucode_dbg_size, val;



	/* GMU TCM data dumped through AHB */

	gmu_core_dev_snapshot(device, snapshot);
@@ -1946,6 +1958,12 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, 


		/* registers dumped through DBG AHB */

		a6xx_snapshot_dbgahb_regs(device, snapshot);



		/* if SMMU is stalled we don't run crash dump */

		kgsl_regread(device, A6XX_RBBM_STATUS3, &val);

		if (!(val & BIT(24)))

			memset(a6xx_crashdump_registers.hostptr, 0xaa,

					a6xx_crashdump_registers.size);

	}



	/* Preemption record */
@@ -2235,6 +2253,11 @@ void a6xx_crashdump_init(struct adreno_device *adreno_dev) 
				sizeof(unsigned int);

	}



	/* 16 bytes (2 qwords) for last entry in CD script */

	script_size += 16;

	/* Increment data size to store last entry in CD */

	data_size += sizeof(unsigned int);



	/* Now allocate the script and data buffers */



	/* The script buffers needs 2 extra qwords on the end */
@@ -2294,6 +2317,16 @@ void a6xx_crashdump_init(struct adreno_device *adreno_dev) 


	ptr += _a6xx_crashdump_init_non_ctx_dbgahb(ptr, &offset);



	/* Save CD register end pointer to check CD status completion */

	a6xx_cd_reg_end = a6xx_crashdump_registers.hostptr + offset;



	memset(a6xx_crashdump_registers.hostptr, 0xaa,

			a6xx_crashdump_registers.size);



	/* Program the capturescript to read the last register entry */

	*ptr++ = a6xx_crashdump_registers.gpuaddr + offset;

	*ptr++ = (((uint64_t) A6XX_CP_CRASH_DUMP_STATUS) << 44) | (uint64_t) 1;



	*ptr++ = 0;

	*ptr++ = 0;

}