metag: Cache/TLB handling

#ifndef __ASM_METAG_CACHE_H

#define __ASM_METAG_CACHE_H

/* L1 cache line size (64 bytes) */

#define L1_CACHE_SHIFT		6

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

/* Meta requires large data items to be 8 byte aligned. */

#define ARCH_SLAB_MINALIGN	8

/*

 * With an L2 cache, we may invalidate dirty lines, so we need to ensure DMA

 * buffers have cache line alignment.

 */

#ifdef CONFIG_METAG_L2C

#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES

#else

#define ARCH_DMA_MINALIGN	8

#endif

#define __read_mostly __attribute__((__section__(".data..read_mostly")))

#endif

#ifndef _METAG_CACHEFLUSH_H

#define _METAG_CACHEFLUSH_H

#include <linux/mm.h>

#include <linux/sched.h>

#include <linux/io.h>

#include <asm/l2cache.h>

#include <asm/metag_isa.h>

#include <asm/metag_mem.h>

void metag_cache_probe(void);

void metag_data_cache_flush_all(const void *start);

void metag_code_cache_flush_all(const void *start);

/*

 * Routines to flush physical cache lines that may be used to cache data or code

 * normally accessed via the linear address range supplied. The region flushed

 * must either lie in local or global address space determined by the top bit of

 * the pStart address. If Bytes is >= 4K then the whole of the related cache

 * state will be flushed rather than a limited range.

 */

void metag_data_cache_flush(const void *start, int bytes);

void metag_code_cache_flush(const void *start, int bytes);

#ifdef CONFIG_METAG_META12

/* Write through, virtually tagged, split I/D cache. */

static inline void __flush_cache_all(void)

{

	metag_code_cache_flush_all((void *) PAGE_OFFSET);

	metag_data_cache_flush_all((void *) PAGE_OFFSET);

}

#define flush_cache_all() __flush_cache_all()

/* flush the entire user address space referenced in this mm structure */

static inline void flush_cache_mm(struct mm_struct *mm)

{

	if (mm == current->mm)

		__flush_cache_all();

}

#define flush_cache_dup_mm(mm) flush_cache_mm(mm)

/* flush a range of addresses from this mm */

static inline void flush_cache_range(struct vm_area_struct *vma,

				     unsigned long start, unsigned long end)

{

	flush_cache_mm(vma->vm_mm);

}

static inline void flush_cache_page(struct vm_area_struct *vma,

				    unsigned long vmaddr, unsigned long pfn)

{

	flush_cache_mm(vma->vm_mm);

}

#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE	1

static inline void flush_dcache_page(struct page *page)

{

	metag_data_cache_flush_all((void *) PAGE_OFFSET);

}

#define flush_dcache_mmap_lock(mapping)		do { } while (0)

#define flush_dcache_mmap_unlock(mapping)	do { } while (0)

static inline void flush_icache_page(struct vm_area_struct *vma,

				     struct page *page)

{

	metag_code_cache_flush(page_to_virt(page), PAGE_SIZE);

}

static inline void flush_cache_vmap(unsigned long start, unsigned long end)

{

	metag_data_cache_flush_all((void *) PAGE_OFFSET);

}

static inline void flush_cache_vunmap(unsigned long start, unsigned long end)

{

	metag_data_cache_flush_all((void *) PAGE_OFFSET);

}

#else

/* Write through, physically tagged, split I/D cache. */

#define flush_cache_all()			do { } while (0)

#define flush_cache_mm(mm)			do { } while (0)

#define flush_cache_dup_mm(mm)			do { } while (0)

#define flush_cache_range(vma, start, end)	do { } while (0)

#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)

#define flush_dcache_mmap_lock(mapping)		do { } while (0)

#define flush_dcache_mmap_unlock(mapping)	do { } while (0)

#define flush_icache_page(vma, pg)		do { } while (0)

#define flush_cache_vmap(start, end)		do { } while (0)

#define flush_cache_vunmap(start, end)		do { } while (0)

#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE	1

static inline void flush_dcache_page(struct page *page)

{

	/* FIXME: We can do better than this. All we are trying to do is

	 * make the i-cache coherent, we should use the PG_arch_1 bit like

	 * e.g. powerpc.

	 */

#ifdef CONFIG_SMP

	metag_out32(1, SYSC_ICACHE_FLUSH);

#else

	metag_code_cache_flush_all((void *) PAGE_OFFSET);

#endif

}

#endif

/* Push n pages at kernel virtual address and clear the icache */

static inline void flush_icache_range(unsigned long address,

				      unsigned long endaddr)

{

#ifdef CONFIG_SMP

	metag_out32(1, SYSC_ICACHE_FLUSH);

#else

	metag_code_cache_flush((void *) address, endaddr - address);

#endif

}

static inline void flush_cache_sigtramp(unsigned long addr, int size)

{

	/*

	 * Flush the icache in case there was previously some code

	 * fetched from this address, perhaps a previous sigtramp.

	 *

	 * We don't need to flush the dcache, it's write through and

	 * we just wrote the sigtramp code through it.

	 */

#ifdef CONFIG_SMP

	metag_out32(1, SYSC_ICACHE_FLUSH);

#else

	metag_code_cache_flush((void *) addr, size);

#endif

}

#ifdef CONFIG_METAG_L2C

/*

 * Perform a single specific CACHEWD operation on an address, masking lower bits

 * of address first.

 */

static inline void cachewd_line(void *addr, unsigned int data)

{

	unsigned long masked = (unsigned long)addr & -0x40;

	__builtin_meta2_cachewd((void *)masked, data);

}

/* Perform a certain CACHEW op on each cache line in a range */

static inline void cachew_region_op(void *start, unsigned long size,

				    unsigned int op)

{

	unsigned long offset = (unsigned long)start & 0x3f;

	int i;

	if (offset) {

		size += offset;

		start -= offset;

	}

	i = (size - 1) >> 6;

	do {

		__builtin_meta2_cachewd(start, op);

		start += 0x40;

	} while (i--);

}

/* prevent write fence and flushbacks being reordered in L2 */

static inline void l2c_fence_flush(void *addr)

{

	/*

	 * Synchronise by reading back and re-flushing.

	 * It is assumed this access will miss, as the caller should have just

	 * flushed the cache line.

	 */

	(void)(volatile u8 *)addr;

	cachewd_line(addr, CACHEW_FLUSH_L1D_L2);

}

/* prevent write fence and writebacks being reordered in L2 */

static inline void l2c_fence(void *addr)

{

	/*

	 * A write back has occurred, but not necessarily an invalidate, so the

	 * readback in l2c_fence_flush() would hit in the cache and have no

	 * effect. Therefore fully flush the line first.

	 */

	cachewd_line(addr, CACHEW_FLUSH_L1D_L2);

	l2c_fence_flush(addr);

}

/* Used to keep memory consistent when doing DMA. */

static inline void flush_dcache_region(void *start, unsigned long size)

{

	/* metag_data_cache_flush won't flush L2 cache lines if size >= 4096 */

	if (meta_l2c_is_enabled()) {

		cachew_region_op(start, size, CACHEW_FLUSH_L1D_L2);

		if (meta_l2c_is_writeback())

			l2c_fence_flush(start + size - 1);

	} else {

		metag_data_cache_flush(start, size);

	}

}

/* Write back dirty lines to memory (or do nothing if no writeback caches) */

static inline void writeback_dcache_region(void *start, unsigned long size)

{

	if (meta_l2c_is_enabled() && meta_l2c_is_writeback()) {

		cachew_region_op(start, size, CACHEW_WRITEBACK_L1D_L2);

		l2c_fence(start + size - 1);

	}

}

/* Invalidate (may also write back if necessary) */

static inline void invalidate_dcache_region(void *start, unsigned long size)

{

	if (meta_l2c_is_enabled())

		cachew_region_op(start, size, CACHEW_INVALIDATE_L1D_L2);

	else

		metag_data_cache_flush(start, size);

}

#else

#define flush_dcache_region(s, l)	metag_data_cache_flush((s), (l))

#define writeback_dcache_region(s, l)	do {} while (0)

#define invalidate_dcache_region(s, l)	flush_dcache_region((s), (l))

#endif

static inline void copy_to_user_page(struct vm_area_struct *vma,

				     struct page *page, unsigned long vaddr,

				     void *dst, const void *src,

				     unsigned long len)

{

	memcpy(dst, src, len);

	flush_icache_range((unsigned long)dst, (unsigned long)dst + len);

}

static inline void copy_from_user_page(struct vm_area_struct *vma,

				       struct page *page, unsigned long vaddr,

				       void *dst, const void *src,

				       unsigned long len)

{

	memcpy(dst, src, len);

}

#endif /* _METAG_CACHEFLUSH_H */

#ifndef _METAG_L2CACHE_H

#define _METAG_L2CACHE_H

#ifdef CONFIG_METAG_L2C

#include <asm/global_lock.h>

#include <asm/io.h>

/*

 * Store the last known value of pfenable (we don't want prefetch enabled while

 * L2 is off).

 */

extern int l2c_pfenable;

/* defined in arch/metag/drivers/core-sysfs.c */

extern struct sysdev_class cache_sysclass;

static inline void wr_fence(void);

/*

 * Functions for reading of L2 cache configuration.

 */

/* Get raw L2 config register (CORE_CONFIG3) */

static inline unsigned int meta_l2c_config(void)

{

	const unsigned int *corecfg3 = (const unsigned int *)METAC_CORE_CONFIG3;

	return *corecfg3;

}

/* Get whether the L2 is present */

static inline int meta_l2c_is_present(void)

{

	return meta_l2c_config() & METAC_CORECFG3_L2C_HAVE_L2C_BIT;

}

/* Get whether the L2 is configured for write-back instead of write-through */

static inline int meta_l2c_is_writeback(void)

{

	return meta_l2c_config() & METAC_CORECFG3_L2C_MODE_BIT;

}

/* Get whether the L2 is unified instead of separated code/data */

static inline int meta_l2c_is_unified(void)

{

	return meta_l2c_config() & METAC_CORECFG3_L2C_UNIFIED_BIT;

}

/* Get the L2 cache size in bytes */

static inline unsigned int meta_l2c_size(void)

{

	unsigned int size_s;

	if (!meta_l2c_is_present())

		return 0;

	size_s = (meta_l2c_config() & METAC_CORECFG3_L2C_SIZE_BITS)

			>> METAC_CORECFG3_L2C_SIZE_S;

	/* L2CSIZE is in KiB */

	return 1024 << size_s;

}

/* Get the number of ways in the L2 cache */

static inline unsigned int meta_l2c_ways(void)

{

	unsigned int ways_s;

	if (!meta_l2c_is_present())

		return 0;

	ways_s = (meta_l2c_config() & METAC_CORECFG3_L2C_NUM_WAYS_BITS)

			>> METAC_CORECFG3_L2C_NUM_WAYS_S;

	return 0x1 << ways_s;

}

/* Get the line size of the L2 cache */

static inline unsigned int meta_l2c_linesize(void)

{

	unsigned int line_size;

	if (!meta_l2c_is_present())

		return 0;

	line_size = (meta_l2c_config() & METAC_CORECFG3_L2C_LINE_SIZE_BITS)

			>> METAC_CORECFG3_L2C_LINE_SIZE_S;

	switch (line_size) {

	case METAC_CORECFG3_L2C_LINE_SIZE_64B:

		return 64;

	default:

		return 0;

	}

}

/* Get the revision ID of the L2 cache */

static inline unsigned int meta_l2c_revision(void)

{

	return (meta_l2c_config() & METAC_CORECFG3_L2C_REV_ID_BITS)

			>> METAC_CORECFG3_L2C_REV_ID_S;

}

/*

 * Start an initialisation of the L2 cachelines and wait for completion.

 * This should only be done in a LOCK1 or LOCK2 critical section while the L2

 * is disabled.

 */

static inline void _meta_l2c_init(void)

{

	metag_out32(SYSC_L2C_INIT_INIT, SYSC_L2C_INIT);

	while (metag_in32(SYSC_L2C_INIT) == SYSC_L2C_INIT_IN_PROGRESS)

		/* do nothing */;

}

/*

 * Start a writeback of dirty L2 cachelines and wait for completion.

 * This should only be done in a LOCK1 or LOCK2 critical section.

 */

static inline void _meta_l2c_purge(void)

{

	metag_out32(SYSC_L2C_PURGE_PURGE, SYSC_L2C_PURGE);

	while (metag_in32(SYSC_L2C_PURGE) == SYSC_L2C_PURGE_IN_PROGRESS)

		/* do nothing */;

}

/* Set whether the L2 cache is enabled. */

static inline void _meta_l2c_enable(int enabled)

{

	unsigned int enable;

	enable = metag_in32(SYSC_L2C_ENABLE);

	if (enabled)

		enable |= SYSC_L2C_ENABLE_ENABLE_BIT;

	else

		enable &= ~SYSC_L2C_ENABLE_ENABLE_BIT;

	metag_out32(enable, SYSC_L2C_ENABLE);

}

/* Set whether the L2 cache prefetch is enabled. */

static inline void _meta_l2c_pf_enable(int pfenabled)

{

	unsigned int enable;

	enable = metag_in32(SYSC_L2C_ENABLE);

	if (pfenabled)

		enable |= SYSC_L2C_ENABLE_PFENABLE_BIT;

	else

		enable &= ~SYSC_L2C_ENABLE_PFENABLE_BIT;

	metag_out32(enable, SYSC_L2C_ENABLE);

}

/* Return whether the L2 cache is enabled */

static inline int _meta_l2c_is_enabled(void)

{

	return metag_in32(SYSC_L2C_ENABLE) & SYSC_L2C_ENABLE_ENABLE_BIT;

}

/* Return whether the L2 cache prefetch is enabled */

static inline int _meta_l2c_pf_is_enabled(void)

{

	return metag_in32(SYSC_L2C_ENABLE) & SYSC_L2C_ENABLE_PFENABLE_BIT;

}

/* Return whether the L2 cache is enabled */

static inline int meta_l2c_is_enabled(void)

{

	int en;

	/*

	 * There is no need to lock at the moment, as the enable bit is never

	 * intermediately changed, so we will never see an intermediate result.

	 */

	en = _meta_l2c_is_enabled();

	return en;

}

/*

 * Ensure the L2 cache is disabled.

 * Return whether the L2 was previously disabled.

 */

int meta_l2c_disable(void);

/*

 * Ensure the L2 cache is enabled.

 * Return whether the L2 was previously enabled.

 */

int meta_l2c_enable(void);

/* Return whether the L2 cache prefetch is enabled */

static inline int meta_l2c_pf_is_enabled(void)

{

	return l2c_pfenable;

}

/*

 * Set whether the L2 cache prefetch is enabled.

 * Return whether the L2 prefetch was previously enabled.

 */

int meta_l2c_pf_enable(int pfenable);

/*

 * Flush the L2 cache.

 * Return 1 if the L2 is disabled.

 */

int meta_l2c_flush(void);

/*

 * Write back all dirty cache lines in the L2 cache.

 * Return 1 if the L2 is disabled or there isn't any writeback.

 */

static inline int meta_l2c_writeback(void)

{

	unsigned long flags;

	int en;

	/* no need to purge if it's not a writeback cache */

	if (!meta_l2c_is_writeback())

		return 1;

	/*

	 * Purge only works if the L2 is enabled, and involves reading back to

	 * detect completion, so keep this operation atomic with other threads.

	 */

	__global_lock1(flags);

	en = meta_l2c_is_enabled();

	if (likely(en)) {

		wr_fence();

		_meta_l2c_purge();

	}

	__global_unlock1(flags);

	return !en;

}

#else /* CONFIG_METAG_L2C */

#define meta_l2c_config()		0

#define meta_l2c_is_present()		0

#define meta_l2c_is_writeback()		0

#define meta_l2c_is_unified()		0

#define meta_l2c_size()			0

#define meta_l2c_ways()			0

#define meta_l2c_linesize()		0

#define meta_l2c_revision()		0

#define meta_l2c_is_enabled()		0

#define _meta_l2c_pf_is_enabled()	0

#define meta_l2c_pf_is_enabled()	0

#define meta_l2c_disable()		1

#define meta_l2c_enable()		0

#define meta_l2c_pf_enable(X)		0

static inline int meta_l2c_flush(void)

{

	return 1;

}

static inline int meta_l2c_writeback(void)

{

	return 1;

}

#endif /* CONFIG_METAG_L2C */

#endif /* _METAG_L2CACHE_H */

#ifndef __ASM_METAG_TLB_H

#define __ASM_METAG_TLB_H

#include <asm/cacheflush.h>

#include <asm/page.h>

/* Note, read http://lkml.org/lkml/2004/1/15/6 */

#ifdef CONFIG_METAG_META12

#define tlb_start_vma(tlb, vma)						      \

	do {								      \

		if (!tlb->fullmm)					      \

			flush_cache_range(vma, vma->vm_start, vma->vm_end);   \

	} while (0)

#define tlb_end_vma(tlb, vma)						      \

	do {								      \

		if (!tlb->fullmm)					      \

			flush_tlb_range(vma, vma->vm_start, vma->vm_end);     \

	} while (0)

#else

#define tlb_start_vma(tlb, vma)			do { } while (0)

#define tlb_end_vma(tlb, vma)			do { } while (0)

#endif

#define __tlb_remove_tlb_entry(tlb, pte, addr)	do { } while (0)

#define tlb_flush(tlb)				flush_tlb_mm((tlb)->mm)

#include <asm-generic/tlb.h>

#endif

#ifndef __ASM_METAG_TLBFLUSH_H

#define __ASM_METAG_TLBFLUSH_H

#include <linux/io.h>

#include <linux/sched.h>

#include <asm/metag_mem.h>

#include <asm/pgalloc.h>

/*

 * TLB flushing:

 *

 *  - flush_tlb() flushes the current mm struct TLBs

 *  - flush_tlb_all() flushes all processes TLBs

 *  - flush_tlb_mm(mm) flushes the specified mm context TLB's

 *  - flush_tlb_page(vma, vmaddr) flushes one page

 *  - flush_tlb_range(mm, start, end) flushes a range of pages

 *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages

 *  - flush_tlb_pgtables(mm, start, end) flushes a range of page tables

 *

 * FIXME: Meta 2 can flush single TLB entries.

 *

 */

#if defined(CONFIG_METAG_META21) && !defined(CONFIG_SMP)

static inline void __flush_tlb(void)

{

	/* flush TLB entries for just the current hardware thread */

	int thread = hard_processor_id();

	metag_out32(0, (LINSYSCFLUSH_TxMMCU_BASE +

			LINSYSCFLUSH_TxMMCU_STRIDE * thread));

}

#else

static inline void __flush_tlb(void)

{

	/* flush TLB entries for all hardware threads */

	metag_out32(0, LINSYSCFLUSH_MMCU);

}

#endif /* defined(CONFIG_METAG_META21) && !defined(CONFIG_SMP) */

#define flush_tlb() __flush_tlb()

#define flush_tlb_all() __flush_tlb()

#define local_flush_tlb_all() __flush_tlb()

static inline void flush_tlb_mm(struct mm_struct *mm)

{

	if (mm == current->active_mm)

		__flush_tlb();

}

static inline void flush_tlb_page(struct vm_area_struct *vma,

				  unsigned long addr)

{

	flush_tlb_mm(vma->vm_mm);

}

static inline void flush_tlb_range(struct vm_area_struct *vma,

				   unsigned long start, unsigned long end)

{

	flush_tlb_mm(vma->vm_mm);

}

static inline void flush_tlb_pgtables(struct mm_struct *mm,

				      unsigned long start, unsigned long end)

{

	flush_tlb_mm(mm);

}

static inline void flush_tlb_kernel_range(unsigned long start,

					  unsigned long end)

{

	flush_tlb_all();

}

#endif /* __ASM_METAG_TLBFLUSH_H */