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Commit 98cd085e authored by Vinod Koul's avatar Vinod Koul
Browse files

Merge branch 'topic/pl08x' into for-linus

parents 70ef9af7 fcc78541

Documentation/devicetree/bindings/dma/arm-pl08x.txt

+7 −2
Original line number Diff line number Diff line
@@ -3,6 +3,11 @@ 
Required properties:

- compatible: "arm,pl080", "arm,primecell";

	      "arm,pl081", "arm,primecell";

	      "faraday,ftdmac020", "arm,primecell"

- arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded

  in the hardware and must be specified here as <0x0003b080>. This number

  follows the PrimeCell standard numbering using the JEP106 vendor code 0x38

  for Faraday Technology.

- reg: Address range of the PL08x registers

- interrupt: The PL08x interrupt number

- clocks: The clock running the IP core clock
@@ -20,8 +25,8 @@ Optional properties: 
- dma-requests: contains the total number of DMA requests supported by the DMAC

- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32

  64, 128 or 256 bytes are legal values

- memcpy-bus-width: the bus width used for memcpy: 8, 16 or 32 are legal

  values

- memcpy-bus-width: the bus width used for memcpy in bits: 8, 16 or 32 are legal

  values, the Faraday FTDMAC020 can also accept 64 bits



Clients

Required properties:

arch/arm/mach-lpc32xx/phy3250.c

+3 −0
Original line number Diff line number Diff line
@@ -137,6 +137,9 @@ static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch) 
}



static struct pl08x_platform_data pl08x_pd = {

	/* Some reasonable memcpy defaults */

	.memcpy_burst_size = PL08X_BURST_SZ_256,

	.memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,

	.slave_channels = &pl08x_slave_channels[0],

	.num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),

	.get_xfer_signal = pl08x_get_signal,

arch/arm/mach-s3c64xx/pl080.c

+8 −20
Original line number Diff line number Diff line
@@ -137,16 +137,10 @@ static const struct dma_slave_map s3c64xx_dma0_slave_map[] = { 
};



struct pl08x_platform_data s3c64xx_dma0_plat_data = {

	.memcpy_channel = {

		.bus_id = "memcpy",

		.cctl_memcpy =

			(PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT |

			PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT |

			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |

			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT |

			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE |

			PL080_CONTROL_PROT_SYS),

	},

	.memcpy_burst_size = PL08X_BURST_SZ_4,

	.memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,

	.memcpy_prot_buff = true,

	.memcpy_prot_cache = true,

	.lli_buses = PL08X_AHB1,

	.mem_buses = PL08X_AHB1,

	.get_xfer_signal = pl08x_get_xfer_signal,
@@ -238,16 +232,10 @@ static const struct dma_slave_map s3c64xx_dma1_slave_map[] = { 
};



struct pl08x_platform_data s3c64xx_dma1_plat_data = {

	.memcpy_channel = {

		.bus_id = "memcpy",

		.cctl_memcpy =

			(PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT |

			PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT |

			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |

			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT |

			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE |

			PL080_CONTROL_PROT_SYS),

	},

	.memcpy_burst_size = PL08X_BURST_SZ_4,

	.memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,

	.memcpy_prot_buff = true,

	.memcpy_prot_cache = true,

	.lli_buses = PL08X_AHB1,

	.mem_buses = PL08X_AHB1,

	.get_xfer_signal = pl08x_get_xfer_signal,

arch/arm/mach-spear/spear3xx.c

+4 −10
Original line number Diff line number Diff line
@@ -44,16 +44,10 @@ struct pl022_ssp_controller pl022_plat_data = { 


/* dmac device registration */

struct pl08x_platform_data pl080_plat_data = {

	.memcpy_channel = {

		.bus_id = "memcpy",

		.cctl_memcpy =

			(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \

			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \

			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \

			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \

			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \

			PL080_CONTROL_PROT_SYS),

	},

	.memcpy_burst_size = PL08X_BURST_SZ_16,

	.memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,

	.memcpy_prot_buff = true,

	.memcpy_prot_cache = true,

	.lli_buses = PL08X_AHB1,

	.mem_buses = PL08X_AHB1,

	.get_xfer_signal = pl080_get_signal,

arch/arm/mach-spear/spear6xx.c

+4 −10
Original line number Diff line number Diff line
@@ -322,16 +322,10 @@ static struct pl08x_channel_data spear600_dma_info[] = { 
};



static struct pl08x_platform_data spear6xx_pl080_plat_data = {

	.memcpy_channel = {

		.bus_id = "memcpy",

		.cctl_memcpy =

			(PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \

			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \

			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \

			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \

			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \

			PL080_CONTROL_PROT_SYS),

	},

	.memcpy_burst_size = PL08X_BURST_SZ_16,

	.memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,

	.memcpy_prot_buff = true,

	.memcpy_prot_cache = true,

	.lli_buses = PL08X_AHB1,

	.mem_buses = PL08X_AHB1,

	.get_xfer_signal = pl080_get_signal,