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Commit 980eec8b authored by Jacob Shin's avatar Jacob Shin Committed by Borislav Petkov
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EDAC, MCE, AMD: Add MCE decoding support for Family 16h 



Add MCE decoding logic for AMD Family 16h processors.

Boris:

- drop unneeded uu_msgs export
- exit early in cat_mc1_mce and save us an indentation level

Signed-off-by: default avatarJacob Shin <jacob.shin@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@alien8.de>
parent 4a73d3de

drivers/edac/mce_amd.c

+78 −17
Original line number Diff line number Diff line
@@ -64,6 +64,9 @@ EXPORT_SYMBOL_GPL(to_msgs); 
const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };

EXPORT_SYMBOL_GPL(ii_msgs);



/* internal error type */

const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" };



static const char * const f15h_mc1_mce_desc[] = {

	"UC during a demand linefill from L2",

	"Parity error during data load from IC",
@@ -176,7 +179,7 @@ static bool k8_mc0_mce(u16 ec, u8 xec) 
	return f10h_mc0_mce(ec, xec);

}



static bool f14h_mc0_mce(u16 ec, u8 xec)

static bool cat_mc0_mce(u16 ec, u8 xec)

{

	u8 r4	 = R4(ec);

	bool ret = true;
@@ -330,22 +333,28 @@ static bool k8_mc1_mce(u16 ec, u8 xec) 
	return ret;

}



static bool f14h_mc1_mce(u16 ec, u8 xec)

static bool cat_mc1_mce(u16 ec, u8 xec)

{

	u8 r4    = R4(ec);

	bool ret = true;



	if (MEM_ERROR(ec)) {

		if (TT(ec) != 0 || LL(ec) != 1)

			ret = false;

	if (!MEM_ERROR(ec))

		return false;



	if (TT(ec) != TT_INSTR)

		return false;



	if (r4 == R4_IRD)

		pr_cont("Data/tag array parity error for a tag hit.\n");

	else if (r4 == R4_SNOOP)

		pr_cont("Tag error during snoop/victimization.\n");

	else if (xec == 0x0)

		pr_cont("Tag parity error from victim castout.\n");

	else if (xec == 0x2)

		pr_cont("Microcode patch RAM parity error.\n");

	else

		ret = false;

	}



	return ret;

}
@@ -469,6 +478,47 @@ static bool f15h_mc2_mce(u16 ec, u8 xec) 
	return ret;

}



static bool f16h_mc2_mce(u16 ec, u8 xec)

{

	u8 r4 = R4(ec);



	if (!MEM_ERROR(ec))

		return false;



	switch (xec) {

	case 0x04 ... 0x05:

		pr_cont("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O');

		break;



	case 0x09 ... 0x0b:

	case 0x0d ... 0x0f:

		pr_cont("ECC error in L2 tag (%s).\n",

			((r4 == R4_GEN)   ? "BankReq" :

			((r4 == R4_SNOOP) ? "Prb"     : "Fill")));

		break;



	case 0x10 ... 0x19:

	case 0x1b:

		pr_cont("ECC error in L2 data array (%s).\n",

			(((r4 == R4_RD) && !(xec & 0x3)) ? "Hit"  :

			((r4 == R4_GEN)   ? "Attr" :

			((r4 == R4_EVICT) ? "Vict" : "Fill"))));

		break;



	case 0x1c ... 0x1d:

	case 0x1f:

		pr_cont("Parity error in L2 attribute bits (%s).\n",

			((r4 == R4_RD)  ? "Hit"  :

			((r4 == R4_GEN) ? "Attr" : "Fill")));

		break;



	default:

		return false;

	}



	return true;

}



static void decode_mc2_mce(struct mce *m)

{

	u16 ec = EC(m->status);
@@ -546,7 +596,7 @@ static void decode_mc4_mce(struct mce *m) 
		return;



	case 0x19:

		if (boot_cpu_data.x86 == 0x15)

		if (boot_cpu_data.x86 == 0x15 || boot_cpu_data.x86 == 0x16)

			pr_cont("Compute Unit Data Error.\n");

		else

			goto wrong_mc4_mce;
@@ -632,6 +682,10 @@ static void decode_mc6_mce(struct mce *m) 


static inline void amd_decode_err_code(u16 ec)

{

	if (INT_ERROR(ec)) {

		pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec));

		return;

	}



	pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec));
@@ -736,7 +790,7 @@ int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) 
		((m->status & MCI_STATUS_PCC)	? "PCC"	  : "-"),

		((m->status & MCI_STATUS_ADDRV)	? "AddrV" : "-"));



	if (c->x86 == 0x15)

	if (c->x86 == 0x15 || c->x86 == 0x16)

		pr_cont("|%s|%s",

			((m->status & MCI_STATUS_DEFERRED) ? "Deferred" : "-"),

			((m->status & MCI_STATUS_POISON)   ? "Poison"   : "-"));
@@ -768,7 +822,7 @@ static int __init mce_amd_init(void) 
	if (c->x86_vendor != X86_VENDOR_AMD)

		return 0;



	if (c->x86 < 0xf || c->x86 > 0x15)

	if (c->x86 < 0xf || c->x86 > 0x16)

		return 0;



	fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
@@ -802,8 +856,8 @@ static int __init mce_amd_init(void) 


	case 0x14:

		nb_err_cpumask  = 0x3;

		fam_ops->mc0_mce = f14h_mc0_mce;

		fam_ops->mc1_mce = f14h_mc1_mce;

		fam_ops->mc0_mce = cat_mc0_mce;

		fam_ops->mc1_mce = cat_mc1_mce;

		fam_ops->mc2_mce = k8_mc2_mce;

		break;
@@ -814,6 +868,13 @@ static int __init mce_amd_init(void) 
		fam_ops->mc2_mce = f15h_mc2_mce;

		break;



	case 0x16:

		xec_mask = 0x1f;

		fam_ops->mc0_mce = cat_mc0_mce;

		fam_ops->mc1_mce = cat_mc1_mce;

		fam_ops->mc2_mce = f16h_mc2_mce;

		break;



	default:

		printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);

		kfree(fam_ops);

drivers/edac/mce_amd.h

+3 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#define TLB_ERROR(x)			(((x) & 0xFFF0) == 0x0010)

#define MEM_ERROR(x)			(((x) & 0xFF00) == 0x0100)

#define BUS_ERROR(x)			(((x) & 0xF800) == 0x0800)

#define INT_ERROR(x)			(((x) & 0xF4FF) == 0x0400)



#define TT(x)				(((x) >> 2) & 0x3)

#define TT_MSG(x)			tt_msgs[TT(x)]
@@ -25,6 +26,8 @@ 
#define TO_MSG(x)			to_msgs[TO(x)]

#define PP(x)				(((x) >> 9) & 0x3)

#define PP_MSG(x)			pp_msgs[PP(x)]

#define UU(x)				(((x) >> 8) & 0x3)

#define UU_MSG(x)			uu_msgs[UU(x)]



#define R4(x)				(((x) >> 4) & 0xf)

#define R4_MSG(x)			((R4(x) < 9) ?  rrrr_msgs[R4(x)] : "Wrong R4!")