Merge "clk: qcom: dispcc-scuba: Add support for DISPCC clock driver" (97f9bbc4) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/clk/qcom/Kconfig

+19 −0

Original line number	Diff line number	Diff line
		@@ -505,3 +505,22 @@ config SDM_VIDEOCC_LAGOON
		LAGOON devices.
		Say Y if you want to support video devices and functionality such as
		video encode/decode.

		config QM_GCC_SCUBA
		tristate "SCUBA Global Clock Controller"
		select QCOM_GDSC
		depends on COMMON_CLK_QCOM
		help
		Support for the global clock controller on Qualcomm Technologies, Inc
		SCUBA devices.
		Say Y if you want to use peripheral devices such as UART, SPI, I2C,
		USB, SD/eMMC, etc.

		config QM_DISPCC_SCUBA
		tristate "SCUBA Display Clock Controller"
		select QM_GCC_SCUBA
		help
		Support for the display clock controller on Qualcomm Technologies, Inc.
		SCUBA devices.
		Say Y if you want to support display devices and functionality such as
		splash screen.

drivers/clk/qcom/Makefile

+2 −0

Original line number	Diff line number	Diff line
		@@ -49,6 +49,8 @@ obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
		obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
		obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
		obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
		obj-$(CONFIG_QM_DISPCC_SCUBA) += dispcc-scuba.o
		obj-$(CONFIG_QM_GCC_SCUBA) += gcc-scuba.o
		obj-$(CONFIG_SDM_CAMCC_LAGOON) += camcc-lagoon.o
		obj-$(CONFIG_SDM_DEBUGCC_LAGOON) += debugcc-lagoon.o
		obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o

drivers/clk/qcom/dispcc-scuba.c

0 → 100644

+651 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2020, The Linux Foundation. All rights reserved.
		*/

		#include <linux/clk.h>
		#include <linux/clk-provider.h>
		#include <linux/err.h>
		#include <linux/kernel.h>
		#include <linux/module.h>
		#include <linux/of_device.h>
		#include <linux/of.h>
		#include <linux/regmap.h>

		#include <dt-bindings/clock/qcom,dispcc-scuba.h>

		#include "clk-alpha-pll.h"
		#include "clk-branch.h"
		#include "clk-rcg.h"
		#include "clk-regmap.h"
		#include "clk-regmap-divider.h"
		#include "common.h"
		#include "reset.h"
		#include "vdd-level.h"

		static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);

		enum {
		P_BI_TCXO,
		P_CORE_BI_PLL_TEST_SE,
		P_DISP_CC_PLL0_OUT_MAIN,
		P_DSI0_PHY_PLL_OUT_BYTECLK,
		P_DSI0_PHY_PLL_OUT_DSICLK,
		P_DSI1_PHY_PLL_OUT_DSICLK,
		P_GPLL0_OUT_MAIN,
		P_SLEEP_CLK,
		};

		static const struct parent_map disp_cc_parent_map_0[] = {
		{ P_BI_TCXO, 0 },
		{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const disp_cc_parent_names_0[] = {
		"bi_tcxo",
		"dsi0_phy_pll_out_byteclk",
		"core_bi_pll_test_se",
		};

		static const struct parent_map disp_cc_parent_map_1[] = {
		{ P_BI_TCXO, 0 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const disp_cc_parent_names_1[] = {
		"bi_tcxo",
		"core_bi_pll_test_se",
		};
		static const char * const disp_cc_parent_names_1_ao[] = {
		"bi_tcxo_ao",
		"core_bi_pll_test_se",
		};

		static const struct parent_map disp_cc_parent_map_2[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPLL0_OUT_MAIN, 4 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const disp_cc_parent_names_2[] = {
		"bi_tcxo",
		"gcc_disp_gpll0_div_clk_src",
		"core_bi_pll_test_se",
		};

		static const struct parent_map disp_cc_parent_map_3[] = {
		{ P_BI_TCXO, 0 },
		{ P_DISP_CC_PLL0_OUT_MAIN, 1 },
		{ P_GPLL0_OUT_MAIN, 4 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const disp_cc_parent_names_3[] = {
		"bi_tcxo",
		"disp_cc_pll0",
		"gpll0",
		"core_bi_pll_test_se",
		};

		static const struct parent_map disp_cc_parent_map_4[] = {
		{ P_BI_TCXO, 0 },
		{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
		{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const disp_cc_parent_names_4[] = {
		"bi_tcxo",
		"dsi0_phy_pll_out_dsiclk",
		"dsi1_phy_pll_out_dsiclk",
		"core_bi_pll_test_se",
		};

		static const struct parent_map disp_cc_parent_map_5[] = {
		{ P_SLEEP_CLK, 0 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const disp_cc_parent_names_5[] = {
		"chip_sleep_clk",
		"core_bi_pll_test_se",
		};

		static struct pll_vco spark_vco[] = {
		{ 500000000, 1000000000, 2 },
		};

		/* 768MHz configuration */
		static const struct alpha_pll_config disp_cc_pll0_config = {
		.l = 0x28,
		.alpha = 0x0,
		.alpha_en_mask = BIT(24),
		.vco_val = 0x2 << 20,
		.vco_mask = GENMASK(21, 20),
		.main_output_mask = BIT(0),
		.config_ctl_val = 0x4001055B,
		.test_ctl_hi1_val = 0x1,
		.test_ctl_hi_mask = 0x1,
		};

		static struct clk_alpha_pll disp_cc_pll0 = {
		.offset = 0x0,
		.vco_table = spark_vco,
		.num_vco = ARRAY_SIZE(spark_vco),
		.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
		.clkr = {
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_pll0",
		.parent_names = (const char *[]){ "bi_tcxo" },
		.num_parents = 1,
		.ops = &clk_alpha_pll_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 1000000000,
		[VDD_NOMINAL] = 2000000000},
		},
		},
		};

		static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
		.reg = 0x20bc,
		.shift = 0,
		.width = 2,
		.clkr.hw.init = &(struct clk_init_data) {
		.name = "disp_cc_mdss_byte0_div_clk_src",
		.parent_names =
		(const char *[]){ "disp_cc_mdss_byte0_clk_src" },
		.num_parents = 1,
		.flags = CLK_GET_RATE_NOCACHE,
		.ops = &clk_regmap_div_ops,
		},
		};

		static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
		F(19200000, P_BI_TCXO, 1, 0, 0),
		F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0),
		F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
		{ }
		};

		static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
		.cmd_rcgr = 0x2154,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = disp_cc_parent_map_2,
		.freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
		.enable_safe_config = true,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_ahb_clk_src",
		.parent_names = disp_cc_parent_names_2,
		.num_parents = 3,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 19200000,
		[VDD_LOW] = 37500000,
		[VDD_NOMINAL] = 75000000},
		},
		};

		static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
		.cmd_rcgr = 0x20a4,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = disp_cc_parent_map_0,
		.enable_safe_config = true,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_byte0_clk_src",
		.parent_names = disp_cc_parent_names_0,
		.num_parents = 3,
		.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
		.ops = &clk_byte2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 19200000,
		[VDD_LOWER] = 164000000,
		[VDD_LOW] = 187500000},
		},
		};

		static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
		F(19200000, P_BI_TCXO, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
		.cmd_rcgr = 0x20c0,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = disp_cc_parent_map_0,
		.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_esc0_clk_src",
		.parent_names = disp_cc_parent_names_0,
		.num_parents = 3,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 19200000},
		},
		};

		static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
		F(19200000, P_BI_TCXO, 1, 0, 0),
		F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
		F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
		F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
		F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
		{ }
		};

		static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
		.cmd_rcgr = 0x2074,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = disp_cc_parent_map_3,
		.freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
		.enable_safe_config = true,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_mdp_clk_src",
		.parent_names = disp_cc_parent_names_3,
		.num_parents = 4,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 19200000,
		[VDD_LOWER] = 192000000,
		[VDD_LOW] = 256000000,
		[VDD_LOW_L1] = 307200000,
		[VDD_NOMINAL] = 384000000},
		},
		};

		static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
		.cmd_rcgr = 0x205c,
		.mnd_width = 8,
		.hid_width = 5,
		.parent_map = disp_cc_parent_map_4,
		.enable_safe_config = true,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_pclk0_clk_src",
		.parent_names = disp_cc_parent_names_4,
		.num_parents = 4,
		.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
		.ops = &clk_pixel_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 19200000,
		[VDD_LOWER] = 183310056,
		[VDD_LOW] = 250000000},
		},
		};

		static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
		.cmd_rcgr = 0x208c,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = disp_cc_parent_map_1,
		.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
		.enable_safe_config = true,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_vsync_clk_src",
		.parent_names = disp_cc_parent_names_1,
		.num_parents = 2,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 19200000},
		},
		};

		static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
		F(32764, P_SLEEP_CLK, 1, 0, 0),
		{ }
		};

		static struct clk_rcg2 disp_cc_sleep_clk_src = {
		.cmd_rcgr = 0x6050,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = disp_cc_parent_map_5,
		.freq_tbl = ftbl_disp_cc_sleep_clk_src,
		.enable_safe_config = true,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "disp_cc_sleep_clk_src",
		.parent_names = disp_cc_parent_names_5,
		.num_parents = 2,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 32764},
		},
		};

		static struct clk_rcg2 disp_cc_xo_clk_src = {
		.cmd_rcgr = 0x6034,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = disp_cc_parent_map_1,
		.freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "disp_cc_xo_clk_src",
		.parent_names = disp_cc_parent_names_1_ao,
		.num_parents = 2,
		.ops = &clk_rcg2_ops,
		},
		};

		static struct clk_branch disp_cc_mdss_ahb_clk = {
		.halt_reg = 0x2044,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x2044,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_ahb_clk",
		.parent_names = (const char *[]){
		"disp_cc_mdss_ahb_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch disp_cc_mdss_byte0_clk = {
		.halt_reg = 0x201c,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x201c,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_byte0_clk",
		.parent_names = (const char *[]){
		"disp_cc_mdss_byte0_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
		.halt_reg = 0x2020,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x2020,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_byte0_intf_clk",
		.parent_names = (const char *[]){
		"disp_cc_mdss_byte0_div_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch disp_cc_mdss_esc0_clk = {
		.halt_reg = 0x2024,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x2024,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_esc0_clk",
		.parent_names = (const char *[]){
		"disp_cc_mdss_esc0_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch disp_cc_mdss_mdp_clk = {
		.halt_reg = 0x2008,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x2008,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_mdp_clk",
		.parent_names = (const char *[]){
		"disp_cc_mdss_mdp_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
		.halt_reg = 0x2010,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x2010,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_mdp_lut_clk",
		.parent_names = (const char *[]){
		"disp_cc_mdss_mdp_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
		.halt_reg = 0x4004,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x4004,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_non_gdsc_ahb_clk",
		.parent_names = (const char *[]){
		"disp_cc_mdss_ahb_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch disp_cc_mdss_pclk0_clk = {
		.halt_reg = 0x2004,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x2004,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_pclk0_clk",
		.parent_names = (const char *[]){
		"disp_cc_mdss_pclk0_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch disp_cc_mdss_vsync_clk = {
		.halt_reg = 0x2018,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x2018,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_mdss_vsync_clk",
		.parent_names = (const char *[]){
		"disp_cc_mdss_vsync_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch disp_cc_sleep_clk = {
		.halt_reg = 0x6068,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x6068,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_sleep_clk",
		.parent_names = (const char *[]){
		"disp_cc_sleep_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch disp_cc_xo_clk = {
		.halt_reg = 0x604c,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x604c,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "disp_cc_xo_clk",
		.parent_names = (const char *[]){
		"disp_cc_xo_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_IS_CRITICAL \| CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_regmap *disp_cc_scuba_clocks[] = {
		[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
		[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
		[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
		[DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
		[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
		[DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
		[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
		[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
		[DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
		[DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
		[DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
		[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
		[DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
		[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
		[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
		[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
		[DISP_CC_PLL0] = &disp_cc_pll0.clkr,
		[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
		[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
		[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,
		[DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,
		};

		static const struct regmap_config disp_cc_scuba_regmap_config = {
		.reg_bits = 32,
		.reg_stride = 4,
		.val_bits = 32,
		.max_register = 0x10000,
		.fast_io = true,
		};

		static const struct qcom_cc_desc disp_cc_scuba_desc = {
		.config = &disp_cc_scuba_regmap_config,
		.clks = disp_cc_scuba_clocks,
		.num_clks = ARRAY_SIZE(disp_cc_scuba_clocks),
		};

		static const struct of_device_id disp_cc_scuba_match_table[] = {
		{ .compatible = "qcom,scuba-dispcc" },
		{ }
		};
		MODULE_DEVICE_TABLE(of, disp_cc_scuba_match_table);

		static int disp_cc_scuba_probe(struct platform_device *pdev)
		{
		struct regmap *regmap;
		struct clk *clk;
		int ret;

		vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
		if (IS_ERR(vdd_cx.regulator[0])) {
		if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER)
		dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n");
		return PTR_ERR(vdd_cx.regulator[0]);
		}

		regmap = qcom_cc_map(pdev, &disp_cc_scuba_desc);
		if (IS_ERR(regmap))
		return PTR_ERR(regmap);

		clk = clk_get(&pdev->dev, "cfg_ahb_clk");
		if (IS_ERR(clk)) {
		if (PTR_ERR(clk) != -EPROBE_DEFER)
		dev_err(&pdev->dev, "Unable to get ahb clock handle\n");
		return PTR_ERR(clk);
		}
		clk_put(clk);

		clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);

		ret = qcom_cc_really_probe(pdev, &disp_cc_scuba_desc, regmap);
		if (ret) {
		dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
		return ret;
		}

		dev_info(&pdev->dev, "Registered DISP CC clocks\n");

		return ret;
		}

		static struct platform_driver disp_cc_scuba_driver = {
		.probe = disp_cc_scuba_probe,
		.driver = {
		.name = "dispcc-scuba",
		.of_match_table = disp_cc_scuba_match_table,
		},
		};

		static int __init disp_cc_scuba_init(void)
		{
		return platform_driver_register(&disp_cc_scuba_driver);
		}
		subsys_initcall(disp_cc_scuba_init);

		static void __exit disp_cc_scuba_exit(void)
		{
		platform_driver_unregister(&disp_cc_scuba_driver);
		}
		module_exit(disp_cc_scuba_exit);

		MODULE_DESCRIPTION("QTI DISP_CC SCUBA Driver");
		MODULE_LICENSE("GPL v2");

drivers/clk/qcom/gcc-scuba.c

0 → 100644

+3384 −0

File added.

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include/dt-bindings/clock/qcom,gcc-scuba.h

+76 −89

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Copyright (c) 2019, The Linux Foundation. All rights reserved.
		* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
		*/

		#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SCUBA_H
		@@ -79,17 +79,17 @@
		#define GCC_CPUSS_THROTTLE_CORE_CLK 69
		#define GCC_CPUSS_THROTTLE_XO_CLK 70
		#define GCC_DISP_AHB_CLK 71
		#define GCC_DISP_GPLL0_DIV_CLK_SRC 72
		#define GCC_DISP_HF_AXI_CLK 73
		#define GCC_DISP_THROTTLE_CORE_CLK 74
		#define GCC_DISP_XO_CLK 75
		#define GCC_GP1_CLK 76
		#define GCC_GP1_CLK_SRC 77
		#define GCC_GP2_CLK 78
		#define GCC_GP2_CLK_SRC 79
		#define GCC_GP3_CLK 80
		#define GCC_GP3_CLK_SRC 81
		#define GCC_GPU_BIMC_AXI_CLK_SRC 82
		#define GCC_DISP_GPLL0_CLK_SRC 72
		#define GCC_DISP_GPLL0_DIV_CLK_SRC 73
		#define GCC_DISP_HF_AXI_CLK 74
		#define GCC_DISP_THROTTLE_CORE_CLK 75
		#define GCC_DISP_XO_CLK 76
		#define GCC_GP1_CLK 77
		#define GCC_GP1_CLK_SRC 78
		#define GCC_GP2_CLK 79
		#define GCC_GP2_CLK_SRC 80
		#define GCC_GP3_CLK 81
		#define GCC_GP3_CLK_SRC 82
		#define GCC_GPU_CFG_AHB_CLK 83
		#define GCC_GPU_GPLL0_CLK_SRC 84
		#define GCC_GPU_GPLL0_DIV_CLK_SRC 85
		@@ -98,72 +98,63 @@
		#define GCC_GPU_SNOC_DVM_GFX_CLK 88
		#define GCC_GPU_THROTTLE_CORE_CLK 89
		#define GCC_GPU_THROTTLE_XO_CLK 90
		#define GCC_MSS_VS_CLK 91
		#define GCC_PDM2_CLK 92
		#define GCC_PDM2_CLK_SRC 93
		#define GCC_PDM_AHB_CLK 94
		#define GCC_PDM_XO4_CLK 95
		#define GCC_PWM0_XO512_CLK 96
		#define GCC_QMIP_CAMERA_NRT_AHB_CLK 97
		#define GCC_QMIP_CAMERA_RT_AHB_CLK 98
		#define GCC_QMIP_CPUSS_CFG_AHB_CLK 99
		#define GCC_QMIP_DISP_AHB_CLK 100
		#define GCC_QMIP_GPU_CFG_AHB_CLK 101
		#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 102
		#define GCC_QUPV3_WRAP0_CORE_2X_CLK 103
		#define GCC_QUPV3_WRAP0_CORE_CLK 104
		#define GCC_QUPV3_WRAP0_S0_CLK 105
		#define GCC_QUPV3_WRAP0_S0_CLK_SRC 106
		#define GCC_QUPV3_WRAP0_S1_CLK 107
		#define GCC_QUPV3_WRAP0_S1_CLK_SRC 108
		#define GCC_QUPV3_WRAP0_S2_CLK 109
		#define GCC_QUPV3_WRAP0_S2_CLK_SRC 110
		#define GCC_QUPV3_WRAP0_S3_CLK 111
		#define GCC_QUPV3_WRAP0_S3_CLK_SRC 112
		#define GCC_QUPV3_WRAP0_S4_CLK 113
		#define GCC_QUPV3_WRAP0_S4_CLK_SRC 114
		#define GCC_QUPV3_WRAP0_S5_CLK 115
		#define GCC_QUPV3_WRAP0_S5_CLK_SRC 116
		#define GCC_QUPV3_WRAP_0_M_AHB_CLK 117
		#define GCC_QUPV3_WRAP_0_S_AHB_CLK 118
		#define GCC_SDCC1_AHB_CLK 119
		#define GCC_SDCC1_APPS_CLK 120
		#define GCC_SDCC1_APPS_CLK_SRC 121
		#define GCC_SDCC1_ICE_CORE_CLK 122
		#define GCC_SDCC1_ICE_CORE_CLK_SRC 123
		#define GCC_SDCC2_AHB_CLK 124
		#define GCC_SDCC2_APPS_CLK 125
		#define GCC_SDCC2_APPS_CLK_SRC 126
		#define GCC_SYS_NOC_CPUSS_AHB_CLK 127
		#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 128
		#define GCC_USB30_PRIM_MASTER_CLK 129
		#define GCC_USB30_PRIM_MASTER_CLK_SRC 130
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK 131
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 132
		#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV 133
		#define GCC_USB30_PRIM_SLEEP_CLK 134
		#define GCC_USB3_PRIM_CLKREF_CLK 135
		#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 136
		#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 137
		#define GCC_USB3_PRIM_PHY_PIPE_CLK 138
		#define GCC_VCODEC0_AXI_CLK 139
		#define GCC_VDDA_VS_CLK 140
		#define GCC_VDDCX_VS_CLK 141
		#define GCC_VDDMX_VS_CLK 142
		#define GCC_VENUS_AHB_CLK 143
		#define GCC_VENUS_CTL_AXI_CLK 144
		#define GCC_VIDEO_AHB_CLK 145
		#define GCC_VIDEO_AXI0_CLK 146
		#define GCC_VIDEO_THROTTLE_CORE_CLK 147
		#define GCC_VIDEO_VCODEC0_SYS_CLK 148
		#define GCC_VIDEO_VENUS_CLK_SRC 149
		#define GCC_VIDEO_VENUS_CTL_CLK 150
		#define GCC_VIDEO_XO_CLK 151
		#define GCC_VS_CTRL_AHB_CLK 152
		#define GCC_VS_CTRL_CLK 153
		#define GCC_VS_CTRL_CLK_SRC 154
		#define GCC_VSENSOR_CLK_SRC 155
		#define GCC_WCSS_VS_CLK 156
		#define GCC_PDM2_CLK 91
		#define GCC_PDM2_CLK_SRC 92
		#define GCC_PDM_AHB_CLK 93
		#define GCC_PDM_XO4_CLK 94
		#define GCC_PWM0_XO512_CLK 95
		#define GCC_QMIP_CAMERA_NRT_AHB_CLK 96
		#define GCC_QMIP_CAMERA_RT_AHB_CLK 97
		#define GCC_QMIP_CPUSS_CFG_AHB_CLK 98
		#define GCC_QMIP_DISP_AHB_CLK 99
		#define GCC_QMIP_GPU_CFG_AHB_CLK 100
		#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 101
		#define GCC_QUPV3_WRAP0_CORE_2X_CLK 102
		#define GCC_QUPV3_WRAP0_CORE_CLK 103
		#define GCC_QUPV3_WRAP0_S0_CLK 104
		#define GCC_QUPV3_WRAP0_S0_CLK_SRC 105
		#define GCC_QUPV3_WRAP0_S1_CLK 106
		#define GCC_QUPV3_WRAP0_S1_CLK_SRC 107
		#define GCC_QUPV3_WRAP0_S2_CLK 108
		#define GCC_QUPV3_WRAP0_S2_CLK_SRC 109
		#define GCC_QUPV3_WRAP0_S3_CLK 110
		#define GCC_QUPV3_WRAP0_S3_CLK_SRC 111
		#define GCC_QUPV3_WRAP0_S4_CLK 112
		#define GCC_QUPV3_WRAP0_S4_CLK_SRC 113
		#define GCC_QUPV3_WRAP0_S5_CLK 114
		#define GCC_QUPV3_WRAP0_S5_CLK_SRC 115
		#define GCC_QUPV3_WRAP_0_M_AHB_CLK 116
		#define GCC_QUPV3_WRAP_0_S_AHB_CLK 117
		#define GCC_SDCC1_AHB_CLK 118
		#define GCC_SDCC1_APPS_CLK 119
		#define GCC_SDCC1_APPS_CLK_SRC 120
		#define GCC_SDCC1_ICE_CORE_CLK 121
		#define GCC_SDCC1_ICE_CORE_CLK_SRC 122
		#define GCC_SDCC2_AHB_CLK 123
		#define GCC_SDCC2_APPS_CLK 124
		#define GCC_SDCC2_APPS_CLK_SRC 125
		#define GCC_SYS_NOC_CPUSS_AHB_CLK 126
		#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 127
		#define GCC_USB30_PRIM_MASTER_CLK 128
		#define GCC_USB30_PRIM_MASTER_CLK_SRC 129
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK 130
		#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 131
		#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV 132
		#define GCC_USB30_PRIM_SLEEP_CLK 133
		#define GCC_USB3_PRIM_CLKREF_CLK 134
		#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 135
		#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 136
		#define GCC_USB3_PRIM_PHY_PIPE_CLK 137
		#define GCC_VCODEC0_AXI_CLK 138
		#define GCC_VENUS_AHB_CLK 139
		#define GCC_VENUS_CTL_AXI_CLK 140
		#define GCC_VIDEO_AHB_CLK 141
		#define GCC_VIDEO_AXI0_CLK 142
		#define GCC_VIDEO_THROTTLE_CORE_CLK 143
		#define GCC_VIDEO_VCODEC0_SYS_CLK 144
		#define GCC_VIDEO_VENUS_CLK_SRC 145
		#define GCC_VIDEO_VENUS_CTL_CLK 146
		#define GCC_VIDEO_XO_CLK 147

		/* GCC resets */
		#define GCC_CAMSS_OPE_BCR 0
		@@ -173,16 +164,12 @@
		#define GCC_MMSS_BCR 4
		#define GCC_PDM_BCR 5
		#define GCC_QUPV3_WRAPPER_0_BCR 6
		#define GCC_QUPV3_WRAPPER_1_BCR 7
		#define GCC_QUSB2PHY_PRIM_BCR 8
		#define GCC_QUSB2PHY_SEC_BCR 9
		#define GCC_SDCC1_BCR 10
		#define GCC_SDCC2_BCR 11
		#define GCC_USB30_PRIM_BCR 12
		#define GCC_USB_PHY_CFG_AHB2PHY_BCR 13
		#define GCC_VCODEC0_BCR 14
		#define GCC_VENUS_BCR 15
		#define GCC_VIDEO_INTERFACE_BCR 16
		#define GCC_VS_BCR 17
		#define GCC_SDCC1_BCR 7
		#define GCC_SDCC2_BCR 8
		#define GCC_USB30_PRIM_BCR 9
		#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10
		#define GCC_VCODEC0_BCR 11
		#define GCC_VENUS_BCR 12
		#define GCC_VIDEO_INTERFACE_BCR 13

		#endif