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Commit 97b08340 authored by Sankeerth Billakanti's avatar Sankeerth Billakanti Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: vote for the QLINK clk on lagoon 

The dp-usb3 combo phy power is controlled by the QLINK ARC.
If QLINK ARC is not enabled, the ref_clk for the phy is
powered-down. This was causing the DP pll to not lock
sometimes and causing display blankout or flickers. This
change will vote for the QLINK ARC to power the ref clk for
the dp-usb3 combo phy.

Change-Id: I2a70e5a197096dcc0330541c761130afa2e7e4ee
parent 5a298b18

qcom/lagoon-sde-pll.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ 
			"ln_tx1_base", "gdsc_base";



		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

			 <&rpmhcc RPMH_CXO_CLK>,

			 <&rpmhcc RPMH_QLINK_CLK>,

			 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,

			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

		clock-names = "iface_clk", "ref_clk_src", "ref_clk",

qcom/lagoon-sde.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -483,7 +483,7 @@ 


	clocks =	<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,

			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

			<&rpmhcc RPMH_CXO_CLK>,

			<&rpmhcc RPMH_QLINK_CLK>,

			<&gcc GCC_USB3_PRIM_CLKREF_CLK>,

			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

			<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,