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Commit 97a25326 authored by Raghu Vatsavayi's avatar Raghu Vatsavayi Committed by David S. Miller
Browse files

liquidio CN23XX: fix for new check patch errors



New checkpatch script shows some errors with pre-existing
driver. This patch provides fix for those errors.

Signed-off-by: default avatarRaghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com>
Signed-off-by: default avatarDerek Chickles <derek.chickles@caviumnetworks.com>
Signed-off-by: default avatarSatanand Burla <satananda.burla@caviumnetworks.com>
Signed-off-by: default avatarFelix Manlunas <felix.manlunas@caviumnetworks.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 50579d3d
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+6 −6
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@

#define     CN23XX_CONFIG_SRIOV_BAR_START	   0x19C
#define     CN23XX_CONFIG_SRIOV_BARX(i)		\
		(CN23XX_CONFIG_SRIOV_BAR_START + (i * 4))
		(CN23XX_CONFIG_SRIOV_BAR_START + ((i) * 4))
#define     CN23XX_CONFIG_SRIOV_BAR_PF		   0x08
#define     CN23XX_CONFIG_SRIOV_BAR_64BIT	   0x04
#define     CN23XX_CONFIG_SRIOV_BAR_IO		   0x01
@@ -508,7 +508,7 @@
/* 4 Registers (64 - bit) */
#define    CN23XX_SLI_S2M_PORT_CTL_START         0x23D80
#define    CN23XX_SLI_S2M_PORTX_CTL(port)	\
		(CN23XX_SLI_S2M_PORT_CTL_START + (port * 0x10))
		(CN23XX_SLI_S2M_PORT_CTL_START + ((port) * 0x10))

#define    CN23XX_SLI_MAC_NUMBER                 0x20050

@@ -549,26 +549,26 @@
 * Provides DMA Engine Queue Enable
 */
#define    CN23XX_DPI_DMA_ENG0_ENB        0x0001df0000000080ULL
#define    CN23XX_DPI_DMA_ENG_ENB(eng) (CN23XX_DPI_DMA_ENG0_ENB + (eng * 8))
#define    CN23XX_DPI_DMA_ENG_ENB(eng) (CN23XX_DPI_DMA_ENG0_ENB + ((eng) * 8))

/* 8 register (64-bit) - DPI_DMA(0..7)_REQQ_CTL
 * Provides control bits for transaction on 8 Queues
 */
#define    CN23XX_DPI_DMA_REQQ0_CTL       0x0001df0000000180ULL
#define    CN23XX_DPI_DMA_REQQ_CTL(q_no)	\
		(CN23XX_DPI_DMA_REQQ0_CTL + (q_no * 8))
		(CN23XX_DPI_DMA_REQQ0_CTL + ((q_no) * 8))

/* 6 register (64-bit) - DPI_ENG(0..5)_BUF
 * Provides DMA Engine FIFO (Queue) Size
 */
#define    CN23XX_DPI_DMA_ENG0_BUF        0x0001df0000000880ULL
#define    CN23XX_DPI_DMA_ENG_BUF(eng)   \
		(CN23XX_DPI_DMA_ENG0_BUF + (eng * 8))
		(CN23XX_DPI_DMA_ENG0_BUF + ((eng) * 8))

/* 4 Registers (64-bit) */
#define    CN23XX_DPI_SLI_PRT_CFG_START   0x0001df0000000900ULL
#define    CN23XX_DPI_SLI_PRTX_CFG(port)        \
		(CN23XX_DPI_SLI_PRT_CFG_START + (port * 0x8))
		(CN23XX_DPI_SLI_PRT_CFG_START + ((port) * 0x8))

/* Masks for DPI_DMA_CONTROL Register */
#define    CN23XX_DPI_DMA_COMMIT_MODE     BIT_ULL(58)
+6 −6
Original line number Diff line number Diff line
@@ -438,10 +438,10 @@
#define    CN6XXX_SLI_S2M_PORT0_CTL              0x3D80
#define    CN6XXX_SLI_S2M_PORT1_CTL              0x3D90
#define    CN6XXX_SLI_S2M_PORTX_CTL(port)        \
	(CN6XXX_SLI_S2M_PORT0_CTL + (port * 0x10))
	(CN6XXX_SLI_S2M_PORT0_CTL + ((port) * 0x10))

#define    CN6XXX_SLI_INT_ENB64(port)            \
	(CN6XXX_SLI_INT_ENB64_PORT0 + (port * 0x10))
	(CN6XXX_SLI_INT_ENB64_PORT0 + ((port) * 0x10))

#define    CN6XXX_SLI_MAC_NUMBER                 0x3E00

@@ -453,7 +453,7 @@
#define    CN6XXX_PCI_BAR1_OFFSET                  0x8

#define    CN6XXX_BAR1_REG(idx, port) \
		(CN6XXX_BAR1_INDEX_START + (port * CN6XXX_PEM_OFFSET) + \
		(CN6XXX_BAR1_INDEX_START + ((port) * CN6XXX_PEM_OFFSET) + \
		(CN6XXX_PCI_BAR1_OFFSET * (idx)))

/*############################ DPI #########################*/
@@ -471,17 +471,17 @@
#define    CN6XXX_DPI_DMA_ENG0_ENB        0x0001df0000000080ULL

#define    CN6XXX_DPI_DMA_ENG_ENB(q_no)   \
	(CN6XXX_DPI_DMA_ENG0_ENB + (q_no * 8))
	(CN6XXX_DPI_DMA_ENG0_ENB + ((q_no) * 8))

#define    CN6XXX_DPI_DMA_ENG0_BUF        0x0001df0000000880ULL

#define    CN6XXX_DPI_DMA_ENG_BUF(q_no)   \
	(CN6XXX_DPI_DMA_ENG0_BUF + (q_no * 8))
	(CN6XXX_DPI_DMA_ENG0_BUF + ((q_no) * 8))

#define    CN6XXX_DPI_SLI_PRT0_CFG        0x0001df0000000900ULL
#define    CN6XXX_DPI_SLI_PRT1_CFG        0x0001df0000000908ULL
#define    CN6XXX_DPI_SLI_PRTX_CFG(port)        \
	(CN6XXX_DPI_SLI_PRT0_CFG + (port * 0x10))
	(CN6XXX_DPI_SLI_PRT0_CFG + ((port) * 0x10))

#define    CN6XXX_DPI_DMA_COMMIT_MODE     BIT_ULL(58)
#define    CN6XXX_DPI_DMA_PKT_HP          BIT_ULL(57)
+1 −1
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ static void lio_cn68xx_setup_pkt_ctl_regs(struct octeon_device *oct)
	pktctl = octeon_read_csr64(oct, CN6XXX_SLI_PKT_CTL);

	/* 68XX specific */
	max_oqs = CFG_GET_OQ_MAX_Q(CHIP_FIELD(oct, cn6xxx, conf));
	max_oqs = CFG_GET_OQ_MAX_Q(CHIP_CONF(oct, cn6xxx));
	tx_pipe  = octeon_read_csr64(oct, CN68XX_SLI_TX_PIPE);
	tx_pipe &= 0xffffffffff00ffffULL; /* clear out NUMP field */
	tx_pipe |= max_oqs << 16; /* put max_oqs in NUMP field */
+4 −5
Original line number Diff line number Diff line
@@ -70,7 +70,6 @@ enum {
	INTERFACE_MODE_MIXED,
};

#define ARRAY_LENGTH(a) (sizeof(a) / sizeof((a)[0]))
#define OCT_ETHTOOL_REGDUMP_LEN  4096
#define OCT_ETHTOOL_REGDUMP_LEN_23XX  (4096 * 11)
#define OCT_ETHTOOL_REGSVER  1
@@ -255,14 +254,14 @@ lio_ethtool_get_channels(struct net_device *dev,
	u32 max_rx = 0, max_tx = 0, tx_count = 0, rx_count = 0;

	if (OCTEON_CN6XXX(oct)) {
		struct octeon_config *conf6x = CHIP_FIELD(oct, cn6xxx, conf);
		struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx);

		max_rx = CFG_GET_OQ_MAX_Q(conf6x);
		max_tx = CFG_GET_IQ_MAX_Q(conf6x);
		rx_count = CFG_GET_NUM_RXQS_NIC_IF(conf6x, lio->ifidx);
		tx_count = CFG_GET_NUM_TXQS_NIC_IF(conf6x, lio->ifidx);
	} else if (OCTEON_CN23XX_PF(oct)) {
		struct octeon_config *conf23 = CHIP_FIELD(oct, cn23xx_pf, conf);
		struct octeon_config *conf23 = CHIP_CONF(oct, cn23xx_pf);

		max_rx = CFG_GET_OQ_MAX_Q(conf23);
		max_tx = CFG_GET_IQ_MAX_Q(conf23);
@@ -585,14 +584,14 @@ lio_ethtool_get_ringparam(struct net_device *netdev,
	    rx_pending = 0;

	if (OCTEON_CN6XXX(oct)) {
		struct octeon_config *conf6x = CHIP_FIELD(oct, cn6xxx, conf);
		struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx);

		tx_max_pending = CN6XXX_MAX_IQ_DESCRIPTORS;
		rx_max_pending = CN6XXX_MAX_OQ_DESCRIPTORS;
		rx_pending = CFG_GET_NUM_RX_DESCS_NIC_IF(conf6x, lio->ifidx);
		tx_pending = CFG_GET_NUM_TX_DESCS_NIC_IF(conf6x, lio->ifidx);
	} else if (OCTEON_CN23XX_PF(oct)) {
		struct octeon_config *conf23 = CHIP_FIELD(oct, cn23xx_pf, conf);
		struct octeon_config *conf23 = CHIP_CONF(oct, cn23xx_pf);

		tx_max_pending = CN23XX_MAX_IQ_DESCRIPTORS;
		rx_max_pending = CN23XX_MAX_OQ_DESCRIPTORS;
+3 −12
Original line number Diff line number Diff line
@@ -48,9 +48,6 @@ MODULE_PARM_DESC(ddr_timeout,

#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)

#define INCR_INSTRQUEUE_PKT_COUNT(octeon_dev_ptr, iq_no, field, count)  \
	(octeon_dev_ptr->instr_queue[iq_no]->stats.field += count)

static int debug = -1;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "NETIF_MSG debug bits");
@@ -59,10 +56,6 @@ static char fw_type[LIO_MAX_FW_TYPE_LEN];
module_param_string(fw_type, fw_type, sizeof(fw_type), 0000);
MODULE_PARM_DESC(fw_type, "Type of firmware to be loaded. Default \"nic\"");

static int conf_type;
module_param(conf_type, int, 0);
MODULE_PARM_DESC(conf_type, "select octeon configuration 0 default 1 ovs");

static int ptp_enable = 1;

/* Bit mask values for lio->ifstate */
@@ -3726,7 +3719,7 @@ static int liquidio_set_vf_link_state(struct net_device *netdev, int vfidx,
	return 0;
}

static struct net_device_ops lionetdevops = {
static const struct net_device_ops lionetdevops = {
	.ndo_open		= liquidio_open,
	.ndo_stop		= liquidio_stop,
	.ndo_start_xmit		= liquidio_xmit,
@@ -3747,6 +3740,7 @@ static struct net_device_ops lionetdevops = {
	.ndo_set_vf_vlan	= liquidio_set_vf_vlan,
	.ndo_get_vf_config	= liquidio_get_vf_config,
	.ndo_set_vf_link_state  = liquidio_set_vf_link_state,
	.ndo_select_queue	= select_q
};

/** \brief Entry point for the liquidio module
@@ -3758,7 +3752,7 @@ static int __init liquidio_init(void)

	init_completion(&first_stage);

	octeon_init_device_list(conf_type);
	octeon_init_device_list(OCTEON_CONFIG_TYPE_DEFAULT);

	if (liquidio_init_pci())
		return -EINVAL;
@@ -3979,9 +3973,6 @@ static int setup_nic_devices(struct octeon_device *octeon_dev)

		SET_NETDEV_DEV(netdev, &octeon_dev->pci_dev->dev);

		if (num_iqueues > 1)
			lionetdevops.ndo_select_queue = select_q;

		/* Associate the routines that will handle different
		 * netdev tasks.
		 */
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