Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 97a229f9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-4.11-rc1' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine updates from Vinod Koul:
 "This time we fairly boring and bit small update.

   - Support for Intel iDMA 32-bit hardware
   - deprecate broken support for channel switching in async_tx
   - bunch of updates on stm32-dma
   - Cyclic support for zx dma and making in generic zx dma driver
   - Small updates to bunch of other drivers"

* tag 'dmaengine-4.11-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (29 commits)
  async_tx: deprecate broken support for channel switching
  dmaengine: rcar-dmac: Widen DMA mask to 40 bits
  dmaengine: sun6i: allow build on ARM64 platforms (sun50i)
  dmaengine: Provide a wrapper for memcpy operations
  dmaengine: zx: fix build warning
  dmaengine: dw: we do support Merrifield SoC in PCI mode
  dmaengine: dw: add support of iDMA 32-bit hardware
  dmaengine: dw: introduce register mappings for iDMA 32-bit
  dmaengine: dw: introduce block2bytes() and bytes2block()
  dmaengine: dw: extract dwc_chan_pause() for future use
  dmaengine: dw: replace convert_burst() with one liner
  dmaengine: dw: register IRQ and DMA pool with instance ID
  dmaengine: dw: Fix data corruption in large device to memory transfers
  dmaengine: ste_dma40: indicate granularity on channels
  dmaengine: ste_dma40: indicate directions on channels
  dmaengine: stm32-dma: Add error messages if xlate fails
  dmaengine: dw: pci: remove LPE Audio DMA ID
  dmaengine: stm32-dma: Add max_burst support
  dmaengine: stm32-dma: Add synchronization support
  dmaengine: stm32-dma: Fix residue computation issue in cyclic mode
  ...
parents ff58d005 1ad65115
Loading
Loading
Loading
Loading
+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ What: /sys/devices/platform/hidma-*/chid
		/sys/devices/platform/QCOM8061:*/chid
Date:		Dec 2015
KernelVersion:	4.4
Contact:	"Sinan Kaya <okaya@cudeaurora.org>"
Contact:	"Sinan Kaya <okaya@codeaurora.org>"
Description:
		Contains the ID of the channel within the HIDMA instance.
		It is used to associate a given HIDMA channel with the
+10 −10
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ What: /sys/devices/platform/hidma-mgmt*/chanops/chan*/priority
		/sys/devices/platform/QCOM8060:*/chanops/chan*/priority
Date:		Nov 2015
KernelVersion:	4.4
Contact:	"Sinan Kaya <okaya@cudeaurora.org>"
Contact:	"Sinan Kaya <okaya@codeaurora.org>"
Description:
		Contains either 0 or 1 and indicates if the DMA channel is a
		low priority (0) or high priority (1) channel.
@@ -11,7 +11,7 @@ What: /sys/devices/platform/hidma-mgmt*/chanops/chan*/weight
		/sys/devices/platform/QCOM8060:*/chanops/chan*/weight
Date:		Nov 2015
KernelVersion:	4.4
Contact:	"Sinan Kaya <okaya@cudeaurora.org>"
Contact:	"Sinan Kaya <okaya@codeaurora.org>"
Description:
		Contains 0..15 and indicates the weight of the channel among
		equal priority channels during round robin scheduling.
@@ -20,7 +20,7 @@ What: /sys/devices/platform/hidma-mgmt*/chreset_timeout_cycles
		/sys/devices/platform/QCOM8060:*/chreset_timeout_cycles
Date:		Nov 2015
KernelVersion:	4.4
Contact:	"Sinan Kaya <okaya@cudeaurora.org>"
Contact:	"Sinan Kaya <okaya@codeaurora.org>"
Description:
		Contains the platform specific cycle value to wait after a
		reset command is issued. If the value is chosen too short,
@@ -32,7 +32,7 @@ What: /sys/devices/platform/hidma-mgmt*/dma_channels
		/sys/devices/platform/QCOM8060:*/dma_channels
Date:		Nov 2015
KernelVersion:	4.4
Contact:	"Sinan Kaya <okaya@cudeaurora.org>"
Contact:	"Sinan Kaya <okaya@codeaurora.org>"
Description:
		Contains the number of dma channels supported by one instance
		of HIDMA hardware. The value may change from chip to chip.
@@ -41,7 +41,7 @@ What: /sys/devices/platform/hidma-mgmt*/hw_version_major
		/sys/devices/platform/QCOM8060:*/hw_version_major
Date:		Nov 2015
KernelVersion:	4.4
Contact:	"Sinan Kaya <okaya@cudeaurora.org>"
Contact:	"Sinan Kaya <okaya@codeaurora.org>"
Description:
		Version number major for the hardware.

@@ -49,7 +49,7 @@ What: /sys/devices/platform/hidma-mgmt*/hw_version_minor
		/sys/devices/platform/QCOM8060:*/hw_version_minor
Date:		Nov 2015
KernelVersion:	4.4
Contact:	"Sinan Kaya <okaya@cudeaurora.org>"
Contact:	"Sinan Kaya <okaya@codeaurora.org>"
Description:
		Version number minor for the hardware.

@@ -57,7 +57,7 @@ What: /sys/devices/platform/hidma-mgmt*/max_rd_xactions
		/sys/devices/platform/QCOM8060:*/max_rd_xactions
Date:		Nov 2015
KernelVersion:	4.4
Contact:	"Sinan Kaya <okaya@cudeaurora.org>"
Contact:	"Sinan Kaya <okaya@codeaurora.org>"
Description:
		Contains a value between 0 and 31. Maximum number of
		read transactions that can be issued back to back.
@@ -69,7 +69,7 @@ What: /sys/devices/platform/hidma-mgmt*/max_read_request
		/sys/devices/platform/QCOM8060:*/max_read_request
Date:		Nov 2015
KernelVersion:	4.4
Contact:	"Sinan Kaya <okaya@cudeaurora.org>"
Contact:	"Sinan Kaya <okaya@codeaurora.org>"
Description:
		Size of each read request. The value needs to be a power
		of two and can be between 128 and 1024.
@@ -78,7 +78,7 @@ What: /sys/devices/platform/hidma-mgmt*/max_wr_xactions
		/sys/devices/platform/QCOM8060:*/max_wr_xactions
Date:		Nov 2015
KernelVersion:	4.4
Contact:	"Sinan Kaya <okaya@cudeaurora.org>"
Contact:	"Sinan Kaya <okaya@codeaurora.org>"
Description:
		Contains a value between 0 and 31. Maximum number of
		write transactions that can be issued back to back.
@@ -91,7 +91,7 @@ What: /sys/devices/platform/hidma-mgmt*/max_write_request
		/sys/devices/platform/QCOM8060:*/max_write_request
Date:		Nov 2015
KernelVersion:	4.4
Contact:	"Sinan Kaya <okaya@cudeaurora.org>"
Contact:	"Sinan Kaya <okaya@codeaurora.org>"
Description:
		Size of each write request. The value needs to be a power
		of two and can be between 128 and 1024.
+2 −3
Original line number Diff line number Diff line
@@ -40,8 +40,7 @@ Example:

DMA clients connected to the STM32 DMA controller must use the format
described in the dma.txt file, using a five-cell specifier for each
channel: a phandle plus four integer cells.
The four cells in order are:
channel: a phandle to the DMA controller plus the following four integer cells:

1. The channel id
2. The request line number
@@ -61,7 +60,7 @@ The four cells in order are:
	0x1: medium
	0x2: high
	0x3: very high
5. A 32bit mask specifying the DMA FIFO threshold configuration which are device
4. A 32bit mask specifying the DMA FIFO threshold configuration which are device
   dependent:
 -bit 0-1: Fifo threshold
	0x0: 1/4 full FIFO
+4 −4
Original line number Diff line number Diff line
@@ -157,7 +157,7 @@ config DMA_SUN4I

config DMA_SUN6I
	tristate "Allwinner A31 SoCs DMA support"
	depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST
	depends on MACH_SUN6I || MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
	depends on RESET_CONTROLLER
	select DMA_ENGINE
	select DMA_VIRTUAL_CHANNELS
@@ -458,7 +458,7 @@ config STM32_DMA
	help
	  Enable support for the on-chip DMA controller on STMicroelectronics
	  STM32 MCUs.
	  If you have a board based on such a MCU and wish to use DMA say Y or M
	  If you have a board based on such a MCU and wish to use DMA say Y
	  here.

config S3C24XX_DMAC
@@ -571,12 +571,12 @@ config XILINX_ZYNQMP_DMA
	  Enable support for Xilinx ZynqMP DMA controller.

config ZX_DMA
	tristate "ZTE ZX296702 DMA support"
	tristate "ZTE ZX DMA support"
	depends on ARCH_ZX || COMPILE_TEST
	select DMA_ENGINE
	select DMA_VIRTUAL_CHANNELS
	help
	  Support the DMA engine for ZTE ZX296702 platform devices.
	  Support the DMA engine for ZTE ZX family platform devices.


# driver files
+1 −1
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ obj-$(CONFIG_TI_CPPI41) += cppi41.o
obj-$(CONFIG_TI_DMA_CROSSBAR) += ti-dma-crossbar.o
obj-$(CONFIG_TI_EDMA) += edma.o
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
obj-$(CONFIG_ZX_DMA) += zx296702_dma.o
obj-$(CONFIG_ZX_DMA) += zx_dma.o
obj-$(CONFIG_ST_FDMA) += st_fdma.o

obj-y += qcom/
Loading