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Commit 97928f70 authored by Alan Cox's avatar Alan Cox Committed by David S. Miller
Browse files

atm: [iphase] 64-bit cleanup 



This fixes the most obvious 64-bit problems, but it is still very very
broken in other aspects.

Signed-off-by: default avatarAlan Cox <alan@redhat.com>
Signed-off-by: default avatarChas Williams <chas@cmf.nrl.navy.mil>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 61c33e01

drivers/atm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -294,7 +294,7 @@ config ATM_HORIZON_DEBUG 


config ATM_IA

	tristate "Interphase ATM PCI x575/x525/x531"

	depends on PCI && !64BIT

	depends on PCI

	---help---

	  This is a driver for the Interphase (i)ChipSAR adapter cards

	  which include a variety of variants in term of the size of the

drivers/atm/iphase.c

+10 −13
Original line number Diff line number Diff line
@@ -89,10 +89,6 @@ module_param(IADebugFlag, uint, 0644); 


MODULE_LICENSE("GPL");



#if BITS_PER_LONG != 32

#  error FIXME: this driver only works on 32-bit platforms

#endif



/**************************** IA_LIB **********************************/



static void ia_init_rtn_q (IARTN_Q *que)
@@ -1406,7 +1402,6 @@ static int rx_init(struct atm_dev *dev) 
	struct abr_vc_table  *abr_vc_table; 

	u16 *vc_table;  

	u16 *reass_table;  

        u16 *ptr16;

	int i,j, vcsize_sel;  

	u_short freeq_st_adr;  

	u_short *freeq_start;
@@ -1424,11 +1419,12 @@ static int rx_init(struct atm_dev *dev) 
	iadev->rx_dle_q.start = (struct dle *)dle_addr;

	iadev->rx_dle_q.read = iadev->rx_dle_q.start;  

	iadev->rx_dle_q.write = iadev->rx_dle_q.start;  

	iadev->rx_dle_q.end = (struct dle*)((u32)dle_addr+sizeof(struct dle)*DLE_ENTRIES);  

	iadev->rx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);

	/* the end of the dle q points to the entry after the last  

	DLE that can be used. */  

  

	/* write the upper 20 bits of the start address to rx list address register */  

	/* We know this is 32bit bus addressed so the following is safe */

	writel(iadev->rx_dle_dma & 0xfffff000,

	       iadev->dma + IPHASE5575_RX_LIST_ADDR);  

	IF_INIT(printk("Tx Dle list addr: 0x%08x value: 0x%0x\n",
@@ -1582,11 +1578,12 @@ static int rx_init(struct atm_dev *dev) 
	   Set Packet Aging Interval count register to overflow in about 4 us

 	*/  

        writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );

        ptr16 = (u16*)j;

        i = ((u32)ptr16 >> 6) & 0xff;

	ptr16  += j - 1;

	i |=(((u32)ptr16 << 2) & 0xff00);



        i = (j >> 6) & 0xFF;

        j += 2 * (j - 1);

        i |= ((j << 2) & 0xFF00);

        writew(i, iadev->reass_reg+TMOUT_RANGE);



        /* initiate the desc_tble */

        for(i=0; i<iadev->num_tx_desc;i++)

            iadev->desc_tbl[i].timestamp = 0;
@@ -1909,7 +1906,7 @@ static int tx_init(struct atm_dev *dev) 
	iadev->tx_dle_q.start = (struct dle*)dle_addr;  

	iadev->tx_dle_q.read = iadev->tx_dle_q.start;  

	iadev->tx_dle_q.write = iadev->tx_dle_q.start;  

	iadev->tx_dle_q.end = (struct dle*)((u32)dle_addr+sizeof(struct dle)*DLE_ENTRIES);  

	iadev->tx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);



	/* write the upper 20 bits of the start address to tx list address register */  

	writel(iadev->tx_dle_dma & 0xfffff000,
@@ -2902,7 +2899,7 @@ static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb) { 
                 dev_kfree_skb_any(skb);

          return 0;

        }

        if ((u32)skb->data & 3) {

        if ((unsigned long)skb->data & 3) {

           printk("Misaligned SKB\n");

           if (vcc->pop)

                 vcc->pop(vcc, skb);