Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 977d29f8 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'sunxi-core-for-4.18' of... 

Merge tag 'sunxi-core-for-4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/soc

Allwinner core changes for 4.18

The A83t, unlike the other Allwinner SoCs, cannot use PSCI because of a
silicon bug. As such, we needed to have some smp_ops in order to bringup
the various cores (and clusters) found on this SoC.

* tag 'sunxi-core-for-4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux

:
  ARM: sun8i: smp: Add support for A83T
  ARM: sun9i: smp: Add is_a83t field
  ARM: sun9i: smp: Rename clusters's power-off
  ARM: shmobile: Convert file to use cntvoff
  ARM: sunxi: Add initialization of CNTVOFF
  ARM: smp: Add initialization of CNTVOFF
  ARM: sunxi: smp: Move assembly code into a file
  ARM: Allow this header to be included by assembly files

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 68fc6c83 6961275e

arch/arm/common/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o 
obj-$(CONFIG_SHARP_LOCOMO)	+= locomo.o

obj-$(CONFIG_SHARP_PARAM)	+= sharpsl_param.o

obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o

obj-$(CONFIG_SMP)		+= secure_cntvoff.o

obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o

obj-$(CONFIG_MCPM)		+= mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o

CFLAGS_REMOVE_mcpm_entry.o	= -pg

arch/arm/common/secure_cntvoff.S

0 → 100644
+32 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2014 Renesas Electronics Corporation

 *

 * Initialization of CNTVOFF register from secure mode

 *

 */



#include <linux/linkage.h>

#include <asm/assembler.h>



ENTRY(secure_cntvoff_init)

	.arch	armv7-a

	/*

	 * CNTVOFF has to be initialized either from non-secure Hypervisor

	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled

	 * then it should be handled by the secure code. The CPU must implement

	 * the virtualization extensions.

	 */

	cps	#MON_MODE

	mrc	p15, 0, r1, c1, c1, 0		/* Get Secure Config */

	orr	r0, r1, #1

	mcr	p15, 0, r0, c1, c1, 0		/* Set Non Secure bit */

	isb

	mov	r0, #0

	mcrr	p15, 4, r0, r0, c14		/* CNTVOFF = 0 */

	isb

	mcr	p15, 0, r1, c1, c1, 0		/* Set Secure bit */

	isb

	cps	#SVC_MODE

	ret	lr

ENDPROC(secure_cntvoff_init)

arch/arm/include/asm/secure_cntvoff.h

0 → 100644
+8 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */



#ifndef __ASMARM_ARCH_CNTVOFF_H

#define __ASMARM_ARCH_CNTVOFF_H



extern void secure_cntvoff_init(void);



#endif

arch/arm/mach-shmobile/common.h

+0 −1
Original line number Diff line number Diff line
@@ -2,7 +2,6 @@ 
#ifndef __ARCH_MACH_COMMON_H

#define __ARCH_MACH_COMMON_H



extern void shmobile_init_cntvoff(void);

extern void shmobile_init_delay(void);

extern void shmobile_boot_vector(void);

extern unsigned long shmobile_boot_fn;

arch/arm/mach-shmobile/headsmp-apmu.S

+1 −21
Original line number Diff line number Diff line
@@ -11,29 +11,9 @@ 
#include <linux/linkage.h>

#include <asm/assembler.h>



ENTRY(shmobile_init_cntvoff)

	/*

	 * CNTVOFF has to be initialized either from non-secure Hypervisor

	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled

	 * then it should be handled by the secure code

	 */

	cps	#MON_MODE

	mrc	p15, 0, r1, c1, c1, 0		/* Get Secure Config */

	orr	r0, r1, #1

	mcr	p15, 0, r0, c1, c1, 0		/* Set Non Secure bit */

	instr_sync

	mov	r0, #0

	mcrr	p15, 4, r0, r0, c14		/* CNTVOFF = 0 */

	instr_sync

	mcr	p15, 0, r1, c1, c1, 0		/* Set Secure bit */

	instr_sync

	cps	#SVC_MODE

	ret	lr

ENDPROC(shmobile_init_cntvoff)



#ifdef CONFIG_SMP

ENTRY(shmobile_boot_apmu)

	bl	shmobile_init_cntvoff

	bl	secure_cntvoff_init

	b	secondary_startup

ENDPROC(shmobile_boot_apmu)

#endif