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Commit 9624dda9 authored by Kevin Hilman's avatar Kevin Hilman
Browse files

Merge tag 'meson-clk-headers-for-4.13' of git://github.com/BayLibre/clk-meson into v4.13/dt64

First round of amlogic clock headers update for v4.13

Only gx related update in this round.
Expose i2s out, spdif out, EE uart gates and SPICC gate.
Un-expose CPU clk which was wrongly copy/pasted from meson8b

* tag 'meson-clk-headers-for-4.13' of git://github.com/BayLibre/clk-meson:
  clk: meson-gxbb: un-export the CPU clock
  clk: meson-gxbb: expose UART clocks
  clk: meson-gxbb: expose SPICC gate
  clk: meson-gxbb: expose spdif master clock
  clk: meson-gxbb: expose i2s master clock
  clk: meson-gxbb: expose spdif clock gates
parents 27f87bd2 f40a8ce9
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+10 −10
Original line number Diff line number Diff line
@@ -171,7 +171,7 @@
 * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
 */
#define CLKID_SYS_PLL		  0
/* CLKID_CPUCLK */
#define CLKID_CPUCLK		  1
/* CLKID_HDMI_PLL */
#define CLKID_FIXED_PLL		  3
/* CLKID_FCLK_DIV2 */
@@ -191,12 +191,12 @@
#define CLKID_ISA		  18
#define CLKID_PL301		  19
#define CLKID_PERIPHS		  20
#define CLKID_SPICC		  21
/* CLKID_SPICC */
/* CLKID_I2C */
/* #define CLKID_SAR_ADC */
#define CLKID_SMART_CARD	  24
/* CLKID_RNG0 */
#define CLKID_UART0		  26
/* CLKID_UART0 */
#define CLKID_SDHC		  27
#define CLKID_STREAM		  28
#define CLKID_ASYNC_FIFO	  29
@@ -209,7 +209,7 @@
/* CLKID_ETH */
#define CLKID_DEMUX		  37
/* CLKID_AIU_GLUE */
#define CLKID_IEC958		  39
/* CLKID_IEC958 */
/* CLKID_I2S_OUT */
#define CLKID_AMCLK		  41
#define CLKID_AIFIFO2		  42
@@ -218,7 +218,7 @@
#define CLKID_ADC		  45
#define CLKID_BLKMV		  46
/* CLKID_AIU */
#define CLKID_UART1		  48
/* CLKID_UART1 */
#define CLKID_G2D		  49
/* CLKID_USB0 */
/* CLKID_USB1 */
@@ -238,7 +238,7 @@
/* CLKID_USB0_DDR_BRIDGE */
#define CLKID_MMC_PCLK		  66
#define CLKID_DVIN		  67
#define CLKID_UART2		  68
/* CLKID_UART2 */
/* #define CLKID_SANA */
#define CLKID_VPU_INTR		  70
#define CLKID_SEC_AHB_AHB3_BRIDGE 71
@@ -251,7 +251,7 @@
#define CLKID_GCLK_VENCI_INT	  78
#define CLKID_DAC_CLK		  79
/* CLKID_AOCLK_GATE */
#define CLKID_IEC958_GATE	  81
/* CLKID_IEC958_GATE */
#define CLKID_ENC480P		  82
#define CLKID_RNG1		  83
#define CLKID_GCLK_VENCI_INT1	  84
@@ -277,13 +277,13 @@
#define CLKID_MALI_1_DIV	 104
/* CLKID_MALI_1	*/
/* CLKID_MALI	*/
#define CLKID_CTS_AMCLK		  107
/* CLKID_CTS_AMCLK */
#define CLKID_CTS_AMCLK_SEL	  108
#define CLKID_CTS_AMCLK_DIV	  109
#define CLKID_CTS_MCLK_I958	  110
/* CLKID_CTS_MCLK_I958 */
#define CLKID_CTS_MCLK_I958_SEL	  111
#define CLKID_CTS_MCLK_I958_DIV	  112
#define CLKID_CTS_I958		  113
/* CLKID_CTS_I958 */

#define NR_CLKS			  114

+9 −1
Original line number Diff line number Diff line
@@ -5,7 +5,6 @@
#ifndef __GXBB_CLKC_H
#define __GXBB_CLKC_H

#define CLKID_CPUCLK		1
#define CLKID_HDMI_PLL		2
#define CLKID_FCLK_DIV2		4
#define CLKID_FCLK_DIV3		5
@@ -13,24 +12,30 @@
#define CLKID_GP0_PLL		9
#define CLKID_CLK81		12
#define CLKID_MPLL2		15
#define CLKID_SPICC		21
#define CLKID_I2C		22
#define CLKID_SAR_ADC		23
#define CLKID_RNG0		25
#define CLKID_UART0		26
#define CLKID_SPI		34
#define CLKID_ETH		36
#define CLKID_AIU_GLUE		38
#define CLKID_IEC958		39
#define CLKID_I2S_OUT		40
#define CLKID_MIXER_IFACE	44
#define CLKID_AIU		47
#define CLKID_UART1		48
#define CLKID_USB0		50
#define CLKID_USB1		51
#define CLKID_USB		55
#define CLKID_HDMI_PCLK		63
#define CLKID_USB1_DDR_BRIDGE	64
#define CLKID_USB0_DDR_BRIDGE	65
#define CLKID_UART2		68
#define CLKID_SANA		69
#define CLKID_GCLK_VENCI_INT0	77
#define CLKID_AOCLK_GATE	80
#define CLKID_IEC958_GATE	81
#define CLKID_AO_I2C		93
#define CLKID_SD_EMMC_A		94
#define CLKID_SD_EMMC_B		95
@@ -42,5 +47,8 @@
#define CLKID_MALI_1_SEL	103
#define CLKID_MALI_1		105
#define CLKID_MALI		106
#define CLKID_CTS_AMCLK		107
#define CLKID_CTS_MCLK_I958	110
#define CLKID_CTS_I958		113

#endif /* __GXBB_CLKC_H */