Merge "ARM: dts: msm: Add QUPV3 SE dt nodes for HSUART on kona" (960433f2) · Commits · e / devices / android_kernel_oneplus_sm7250

arch/arm64/boot/dts/qcom/kona-pinctrl.dtsi

+110 −0

Original line number	Diff line number	Diff line
		@@ -41,6 +41,47 @@
		};
		};

		qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {
		qupv3_se6_ctsrx: qupv3_se6_ctsrx {
		mux {
		pins = "gpio16", "gpio19";
		function = "qup6";
		};

		config {
		pins = "gpio16", "gpio19";
		drive-strength = <2>;
		bias-no-pull;
		};
		};

		qupv3_se6_rts: qupv3_se6_rts {
		mux {
		pins = "gpio17";
		function = "qup6";
		};

		config {
		pins = "gpio17";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		qupv3_se6_tx: qupv3_se6_tx {
		mux {
		pins = "gpio18";
		function = "qup6";
		};

		config {
		pins = "gpio18";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se12_2uart_pins: qupv3_se12_2uart_pins {
		qupv3_se12_2uart_active: qupv3_se12_2uart_active {
		mux {
		@@ -69,6 +110,75 @@
		};
		};

		qupv3_se17_4uart_pins: qupv3_se17_4uart_pins {
		qupv3_se17_ctsrx: qupv3_se17_ctsrx {
		mux {
		pins = "gpio52", "gpio55";
		function = "qup17";
		};

		config {
		pins = "gpio52", "gpio55";
		drive-strength = <2>;
		bias-no-pull;
		};
		};

		qupv3_se17_rts: qupv3_se17_rts {
		mux {
		pins = "gpio53";
		function = "qup17";
		};

		config {
		pins = "gpio53";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		qupv3_se17_tx: qupv3_se17_tx {
		mux {
		pins = "gpio54";
		function = "qup17";
		};

		config {
		pins = "gpio54";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se18_2uart_pins: qupv3_se18_2uart_pins {
		qupv3_se18_rx: qupv3_se18_rx {
		mux {
		pins = "gpio59";
		function = "qup18";
		};

		config {
		pins = "gpio59";
		drive-strength = <2>;
		bias-no-pull;
		};
		};

		qupv3_se18_tx: qupv3_se18_tx {
		mux {
		pins = "gpio58";
		function = "qup18";
		};

		config {
		pins = "gpio58";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		ufs_dev_reset_assert: ufs_dev_reset_assert {
		config {
		pins = "ufs_reset";

arch/arm64/boot/dts/qcom/kona-qupv3.dtsi

+68 −0

Original line number	Diff line number	Diff line
		@@ -39,6 +39,30 @@
		status = "disabled";
		};

		/*
		* HS UART instances. HS UART usecases can be supported on these
		* instances only.
		*/
		qupv3_se6_4uart: qcom,qup_uart@998000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0x998000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
		<&qupv3_se6_tx> ;
		pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
		<&qupv3_se6_tx> ;
		interrupts-extended = <&pdc GIC_SPI 607 0>,
		<&tlmm 19 0>;
		status = "disabled";
		qcom,wakeup-byte = <0xFD>;
		qcom,wrapper-core = <&qupv3_0>;
		};

		/* QUPv3_1 wrapper instance : South_1 QUP */
		qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
		compatible = "qcom,qupv3-geni-se";
		@@ -86,4 +110,48 @@
		qcom,iommu-dma = "disabled";
		};
		};

		/*
		* HS UART : Modem/Audio backup
		*/
		qupv3_se17_4uart: qcom,qup_uart@88c000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0x88c000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
		<&qupv3_se17_tx> ;
		pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
		<&qupv3_se17_tx> ;
		interrupts-extended = <&pdc GIC_SPI 585 0>,
		<&tlmm 55 0>;
		status = "disabled";
		qcom,wakeup-byte = <0xFD>;
		qcom,wrapper-core = <&qupv3_2>;
		};

		/*
		* HS UART : 2-wire Modem
		*/
		qupv3_se18_2uart: qcom,qup_uart@890000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0x890000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;
		pinctrl-1 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;
		interrupts-extended = <&pdc GIC_SPI 586 0>,
		<&tlmm 59 0>;
		status = "disabled";
		qcom,wakeup-byte = <0xFD>;
		qcom,wrapper-core = <&qupv3_2>;
		};
		};