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Commit 952a5db0 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

ARM: dts: Configure omap5 OTG ID pin 



The ID pin GPIO comes from the PMIC. Let's configure it as a GPIO
for the driver to use, and also make sure the PMIC GPIO pin muxing
is correct. The PMIC pad1 and 2 values for omap5-uevm and igepv5 are
0x5a and 0x1b, we only need to clear bit 2 in pad1 register to make
the ID pin GPIO work.

Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 08f9268b

arch/arm/boot/dts/omap5-board-common.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -393,14 +393,23 @@ 
		interrupt-controller;

		#interrupt-cells = <2>;

		ti,system-power-controller;

		ti,mux-pad1 = <0xa1>;

		ti,mux-pad2 = <0x1b>;

		pinctrl-names = "default";

		pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>;



		palmas_gpio: gpio {

			compatible = "ti,palmas-gpio";

			gpio-controller;

			#gpio-cells = <2>;

		};



		extcon_usb3: palmas_usb {

			compatible = "ti,palmas-usb-vid";

			ti,enable-vbus-detection;

			ti,enable-id-detection;

			ti,wakeup;

			id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>;

		};



		clk32kgaudio: palmas_clk32k@1 {

arch/arm/boot/dts/omap5.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -863,7 +863,7 @@ 
			#size-cells = <1>;

			utmi-mode = <2>;

			ranges;

			dwc3@4a030000 {

			dwc3: dwc3@4a030000 {

				compatible = "snps,dwc3";

				reg = <0x4a030000 0x10000>;

				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,