Unverified Commit 94f592f0 authored Aug 02, 2018 by Zong Li Committed by Palmer Dabbelt Aug 13, 2018

RISC-V: Add the directive for alignment of stvec's value



The stvec's value must be 4 byte alignment by specification definition.
These directives avoid to stvec be set the non-alignment value.

Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

parent 62b01943

arch/riscv/kernel/head.S

+2 −0

Original line number	Diff line number	Diff line
		@@ -94,6 +94,7 @@ relocate:
		or a0, a0, a1
		sfence.vma
		csrw sptbr, a0
		.align 2
		1:
		/* Set trap vector to spin forever to help debug */
		la a0, .Lsecondary_park
		@@ -143,6 +144,7 @@ relocate:
		tail smp_callin
		#endif

		.align 2
		.Lsecondary_park:
		/* We lack SMP support or have too many harts, so park this hart */
		wfi