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Commit 94c9fb8c authored by Gaurav Jindal's avatar Gaurav Jindal Committed by Gerrit - the friendly Code Review server
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msm: camera: isp: Dual VFE sync changes 



For lagoon, few changes in CSID and IFE  to handle the
dual vfe sync and halt.
For CSID, while handling the halt, external and internal
core configuration is changed.
For VFE, 3 IFE support is possible with the combinations:
0-1, 1-2, 0-2. This requires changes in dual vfe sync handling.
Also, CSID and IFE versions are updated.
This commit adds the driver header files for the version and
handles the hardware changes in the driver.

CRs-Fixed: 2571273
Change-Id: I48fd3319692cc1044beb20c278cc2fe5676cb668
Signed-off-by: default avatarGaurav Jindal <gjindal@codeaurora.org>
parent bc885682

drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c

+11 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 */



#include <linux/slab.h>
@@ -1576,6 +1576,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_src( 
			else

				vfe_acquire.vfe_in.sync_mode =

				CAM_ISP_HW_SYNC_NONE;

			vfe_acquire.vfe_in.is_dual = csid_res->is_dual_vfe;



			break;

		case CAM_IFE_PIX_PATH_RES_PPP:
@@ -1616,12 +1617,20 @@ static int cam_ife_hw_mgr_acquire_res_ife_src( 
			hw_intf = ife_hw_mgr->ife_devices[

				csid_res->hw_res[i]->hw_intf->hw_idx];



			if (i == CAM_ISP_HW_SPLIT_LEFT &&

				ife_src_res->is_dual_vfe) {

				vfe_acquire.vfe_in.dual_hw_idx =

					ife_ctx->slave_hw_idx;

			}

			/* fill in more acquire information as needed */

			/* slave Camif resource, */

			if (i == CAM_ISP_HW_SPLIT_RIGHT &&

				ife_src_res->is_dual_vfe)

				ife_src_res->is_dual_vfe) {

				vfe_acquire.vfe_in.sync_mode =

				CAM_ISP_HW_SYNC_SLAVE;

				vfe_acquire.vfe_in.dual_hw_idx =

					ife_ctx->master_hw_idx;

			}



			rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv,

					&vfe_acquire,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170_200.h

0 → 100644
+368 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 */



#ifndef _CAM_IFE_CSID_170_200_H_

#define _CAM_IFE_CSID_170_200_H_



#include "cam_ife_csid_core.h"



static struct cam_ife_csid_pxl_reg_offset

	cam_ife_csid_170_200_ipp_reg_offset = {

	.csid_pxl_irq_status_addr            = 0x30,

	.csid_pxl_irq_mask_addr              = 0x34,

	.csid_pxl_irq_clear_addr             = 0x38,

	.csid_pxl_irq_set_addr               = 0x3c,



	.csid_pxl_cfg0_addr                  = 0x200,

	.csid_pxl_cfg1_addr                  = 0x204,

	.csid_pxl_ctrl_addr                  = 0x208,

	.csid_pxl_frm_drop_pattern_addr      = 0x20c,

	.csid_pxl_frm_drop_period_addr       = 0x210,

	.csid_pxl_irq_subsample_pattern_addr = 0x214,

	.csid_pxl_irq_subsample_period_addr  = 0x218,

	.csid_pxl_hcrop_addr                 = 0x21c,

	.csid_pxl_vcrop_addr                 = 0x220,

	.csid_pxl_pix_drop_pattern_addr      = 0x224,

	.csid_pxl_pix_drop_period_addr       = 0x228,

	.csid_pxl_line_drop_pattern_addr     = 0x22c,

	.csid_pxl_line_drop_period_addr      = 0x230,

	.csid_pxl_rst_strobes_addr           = 0x240,

	.csid_pxl_status_addr                = 0x254,

	.csid_pxl_misr_val_addr              = 0x258,

	.csid_pxl_format_measure_cfg0_addr   = 0x270,

	.csid_pxl_format_measure_cfg1_addr   = 0x274,

	.csid_pxl_format_measure0_addr       = 0x278,

	.csid_pxl_format_measure1_addr       = 0x27c,

	.csid_pxl_format_measure2_addr       = 0x280,

	.csid_pxl_timestamp_curr0_sof_addr   = 0x290,

	.csid_pxl_timestamp_curr1_sof_addr   = 0x294,

	.csid_pxl_timestamp_perv0_sof_addr   = 0x298,

	.csid_pxl_timestamp_perv1_sof_addr   = 0x29c,

	.csid_pxl_timestamp_curr0_eof_addr   = 0x2a0,

	.csid_pxl_timestamp_curr1_eof_addr   = 0x2a4,

	.csid_pxl_timestamp_perv0_eof_addr   = 0x2a8,

	.csid_pxl_timestamp_perv1_eof_addr   = 0x2ac,

	/* configurations */

	.pix_store_en_shift_val              = 7,

	.early_eof_en_shift_val              = 29,

	.quad_cfa_bin_en_shift_val           = 30,

	.ccif_violation_en                   = 1,

	.halt_master_sel_en                  = 1,

	.halt_sel_internal_master_val        = 3,

};



static struct cam_ife_csid_pxl_reg_offset

	cam_ife_csid_170_200_ppp_reg_offset = {

	.csid_pxl_irq_status_addr            = 0xa0,

	.csid_pxl_irq_mask_addr              = 0xa4,

	.csid_pxl_irq_clear_addr             = 0xa8,

	.csid_pxl_irq_set_addr               = 0xac,



	.csid_pxl_cfg0_addr                  = 0x700,

	.csid_pxl_cfg1_addr                  = 0x704,

	.csid_pxl_ctrl_addr                  = 0x708,

	.csid_pxl_frm_drop_pattern_addr      = 0x70c,

	.csid_pxl_frm_drop_period_addr       = 0x710,

	.csid_pxl_irq_subsample_pattern_addr = 0x714,

	.csid_pxl_irq_subsample_period_addr  = 0x718,

	.csid_pxl_hcrop_addr                 = 0x71c,

	.csid_pxl_vcrop_addr                 = 0x720,

	.csid_pxl_pix_drop_pattern_addr      = 0x724,

	.csid_pxl_pix_drop_period_addr       = 0x728,

	.csid_pxl_line_drop_pattern_addr     = 0x72c,

	.csid_pxl_line_drop_period_addr      = 0x730,

	.csid_pxl_rst_strobes_addr           = 0x740,

	.csid_pxl_status_addr                = 0x754,

	.csid_pxl_misr_val_addr              = 0x758,

	.csid_pxl_format_measure_cfg0_addr   = 0x770,

	.csid_pxl_format_measure_cfg1_addr   = 0x774,

	.csid_pxl_format_measure0_addr       = 0x778,

	.csid_pxl_format_measure1_addr       = 0x77c,

	.csid_pxl_format_measure2_addr       = 0x780,

	.csid_pxl_timestamp_curr0_sof_addr   = 0x790,

	.csid_pxl_timestamp_curr1_sof_addr   = 0x794,

	.csid_pxl_timestamp_perv0_sof_addr   = 0x798,

	.csid_pxl_timestamp_perv1_sof_addr   = 0x79c,

	.csid_pxl_timestamp_curr0_eof_addr   = 0x7a0,

	.csid_pxl_timestamp_curr1_eof_addr   = 0x7a4,

	.csid_pxl_timestamp_perv0_eof_addr   = 0x7a8,

	.csid_pxl_timestamp_perv1_eof_addr   = 0x7ac,

	/* configurations */

	.pix_store_en_shift_val              = 7,

	.early_eof_en_shift_val              = 29,

	.ccif_violation_en                   = 1,

	.halt_master_sel_en                  = 1,

	.halt_sel_internal_master_val        = 3,

};





static struct cam_ife_csid_rdi_reg_offset

	cam_ife_csid_170_200_rdi_0_reg_offset = {

	.csid_rdi_irq_status_addr                 = 0x40,

	.csid_rdi_irq_mask_addr                   = 0x44,

	.csid_rdi_irq_clear_addr                  = 0x48,

	.csid_rdi_irq_set_addr                    = 0x4c,

	.csid_rdi_cfg0_addr                       = 0x300,

	.csid_rdi_cfg1_addr                       = 0x304,

	.csid_rdi_ctrl_addr                       = 0x308,

	.csid_rdi_frm_drop_pattern_addr           = 0x30c,

	.csid_rdi_frm_drop_period_addr            = 0x310,

	.csid_rdi_irq_subsample_pattern_addr      = 0x314,

	.csid_rdi_irq_subsample_period_addr       = 0x318,

	.csid_rdi_rpp_hcrop_addr                  = 0x31c,

	.csid_rdi_rpp_vcrop_addr                  = 0x320,

	.csid_rdi_rpp_pix_drop_pattern_addr       = 0x324,

	.csid_rdi_rpp_pix_drop_period_addr        = 0x328,

	.csid_rdi_rpp_line_drop_pattern_addr      = 0x32c,

	.csid_rdi_rpp_line_drop_period_addr       = 0x330,

	.csid_rdi_rst_strobes_addr                = 0x340,

	.csid_rdi_status_addr                     = 0x350,

	.csid_rdi_misr_val0_addr                  = 0x354,

	.csid_rdi_misr_val1_addr                  = 0x358,

	.csid_rdi_misr_val2_addr                  = 0x35c,

	.csid_rdi_misr_val3_addr                  = 0x360,

	.csid_rdi_format_measure_cfg0_addr        = 0x370,

	.csid_rdi_format_measure_cfg1_addr        = 0x374,

	.csid_rdi_format_measure0_addr            = 0x378,

	.csid_rdi_format_measure1_addr            = 0x37c,

	.csid_rdi_format_measure2_addr            = 0x380,

	.csid_rdi_timestamp_curr0_sof_addr        = 0x390,

	.csid_rdi_timestamp_curr1_sof_addr        = 0x394,

	.csid_rdi_timestamp_prev0_sof_addr        = 0x398,

	.csid_rdi_timestamp_prev1_sof_addr        = 0x39c,

	.csid_rdi_timestamp_curr0_eof_addr        = 0x3a0,

	.csid_rdi_timestamp_curr1_eof_addr        = 0x3a4,

	.csid_rdi_timestamp_prev0_eof_addr        = 0x3a8,

	.csid_rdi_timestamp_prev1_eof_addr        = 0x3ac,

	.csid_rdi_byte_cntr_ping_addr             = 0x3e0,

	.csid_rdi_byte_cntr_pong_addr             = 0x3e4,

	.ccif_violation_en                        = 1,

};



static struct cam_ife_csid_rdi_reg_offset

	cam_ife_csid_170_200_rdi_1_reg_offset = {

	.csid_rdi_irq_status_addr                 = 0x50,

	.csid_rdi_irq_mask_addr                   = 0x54,

	.csid_rdi_irq_clear_addr                  = 0x58,

	.csid_rdi_irq_set_addr                    = 0x5c,

	.csid_rdi_cfg0_addr                       = 0x400,

	.csid_rdi_cfg1_addr                       = 0x404,

	.csid_rdi_ctrl_addr                       = 0x408,

	.csid_rdi_frm_drop_pattern_addr           = 0x40c,

	.csid_rdi_frm_drop_period_addr            = 0x410,

	.csid_rdi_irq_subsample_pattern_addr      = 0x414,

	.csid_rdi_irq_subsample_period_addr       = 0x418,

	.csid_rdi_rpp_hcrop_addr                  = 0x41c,

	.csid_rdi_rpp_vcrop_addr                  = 0x420,

	.csid_rdi_rpp_pix_drop_pattern_addr       = 0x424,

	.csid_rdi_rpp_pix_drop_period_addr        = 0x428,

	.csid_rdi_rpp_line_drop_pattern_addr      = 0x42c,

	.csid_rdi_rpp_line_drop_period_addr       = 0x430,

	.csid_rdi_rst_strobes_addr                = 0x440,

	.csid_rdi_status_addr                     = 0x450,

	.csid_rdi_misr_val0_addr                  = 0x454,

	.csid_rdi_misr_val1_addr                  = 0x458,

	.csid_rdi_misr_val2_addr                  = 0x45c,

	.csid_rdi_misr_val3_addr                  = 0x460,

	.csid_rdi_format_measure_cfg0_addr        = 0x470,

	.csid_rdi_format_measure_cfg1_addr        = 0x474,

	.csid_rdi_format_measure0_addr            = 0x478,

	.csid_rdi_format_measure1_addr            = 0x47c,

	.csid_rdi_format_measure2_addr            = 0x480,

	.csid_rdi_timestamp_curr0_sof_addr        = 0x490,

	.csid_rdi_timestamp_curr1_sof_addr        = 0x494,

	.csid_rdi_timestamp_prev0_sof_addr        = 0x498,

	.csid_rdi_timestamp_prev1_sof_addr        = 0x49c,

	.csid_rdi_timestamp_curr0_eof_addr        = 0x4a0,

	.csid_rdi_timestamp_curr1_eof_addr        = 0x4a4,

	.csid_rdi_timestamp_prev0_eof_addr        = 0x4a8,

	.csid_rdi_timestamp_prev1_eof_addr        = 0x4ac,

	.csid_rdi_byte_cntr_ping_addr             = 0x4e0,

	.csid_rdi_byte_cntr_pong_addr             = 0x4e4,

	.ccif_violation_en                        = 1,

};



static struct cam_ife_csid_rdi_reg_offset

	cam_ife_csid_170_200_rdi_2_reg_offset = {

	.csid_rdi_irq_status_addr                 = 0x60,

	.csid_rdi_irq_mask_addr                   = 0x64,

	.csid_rdi_irq_clear_addr                  = 0x68,

	.csid_rdi_irq_set_addr                    = 0x6c,

	.csid_rdi_cfg0_addr                       = 0x500,

	.csid_rdi_cfg1_addr                       = 0x504,

	.csid_rdi_ctrl_addr                       = 0x508,

	.csid_rdi_frm_drop_pattern_addr           = 0x50c,

	.csid_rdi_frm_drop_period_addr            = 0x510,

	.csid_rdi_irq_subsample_pattern_addr      = 0x514,

	.csid_rdi_irq_subsample_period_addr       = 0x518,

	.csid_rdi_rpp_hcrop_addr                  = 0x51c,

	.csid_rdi_rpp_vcrop_addr                  = 0x520,

	.csid_rdi_rpp_pix_drop_pattern_addr       = 0x524,

	.csid_rdi_rpp_pix_drop_period_addr        = 0x528,

	.csid_rdi_rpp_line_drop_pattern_addr      = 0x52c,

	.csid_rdi_rpp_line_drop_period_addr       = 0x530,

	.csid_rdi_yuv_chroma_conversion_addr      = 0x534,

	.csid_rdi_rst_strobes_addr                = 0x540,

	.csid_rdi_status_addr                     = 0x550,

	.csid_rdi_misr_val0_addr                  = 0x554,

	.csid_rdi_misr_val1_addr                  = 0x558,

	.csid_rdi_misr_val2_addr                  = 0x55c,

	.csid_rdi_misr_val3_addr                  = 0x560,

	.csid_rdi_format_measure_cfg0_addr        = 0x570,

	.csid_rdi_format_measure_cfg1_addr        = 0x574,

	.csid_rdi_format_measure0_addr            = 0x578,

	.csid_rdi_format_measure1_addr            = 0x57c,

	.csid_rdi_format_measure2_addr            = 0x580,

	.csid_rdi_timestamp_curr0_sof_addr        = 0x590,

	.csid_rdi_timestamp_curr1_sof_addr        = 0x594,

	.csid_rdi_timestamp_prev0_sof_addr        = 0x598,

	.csid_rdi_timestamp_prev1_sof_addr        = 0x59c,

	.csid_rdi_timestamp_curr0_eof_addr        = 0x5a0,

	.csid_rdi_timestamp_curr1_eof_addr        = 0x5a4,

	.csid_rdi_timestamp_prev0_eof_addr        = 0x5a8,

	.csid_rdi_timestamp_prev1_eof_addr        = 0x5ac,

	.csid_rdi_byte_cntr_ping_addr             = 0x5e0,

	.csid_rdi_byte_cntr_pong_addr             = 0x5e4,

	.ccif_violation_en                        = 1,

};



static struct cam_ife_csid_csi2_rx_reg_offset

			cam_ife_csid_170_200_csi2_reg_offset = {

	.csid_csi2_rx_irq_status_addr                 = 0x20,

	.csid_csi2_rx_irq_mask_addr                   = 0x24,

	.csid_csi2_rx_irq_clear_addr                  = 0x28,

	.csid_csi2_rx_irq_set_addr                    = 0x2c,



	/*CSI2 rx control */

	.csid_csi2_rx_cfg0_addr                       = 0x100,

	.csid_csi2_rx_cfg1_addr                       = 0x104,

	.csid_csi2_rx_capture_ctrl_addr               = 0x108,

	.csid_csi2_rx_rst_strobes_addr                = 0x110,

	.csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr   = 0x120,

	.csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr   = 0x124,

	.csid_csi2_rx_captured_short_pkt_0_addr       = 0x128,

	.csid_csi2_rx_captured_short_pkt_1_addr       = 0x12c,

	.csid_csi2_rx_captured_long_pkt_0_addr        = 0x130,

	.csid_csi2_rx_captured_long_pkt_1_addr        = 0x134,

	.csid_csi2_rx_captured_long_pkt_ftr_addr      = 0x138,

	.csid_csi2_rx_captured_cphy_pkt_hdr_addr      = 0x13c,

	.csid_csi2_rx_lane0_misr_addr                 = 0x150,

	.csid_csi2_rx_lane1_misr_addr                 = 0x154,

	.csid_csi2_rx_lane2_misr_addr                 = 0x158,

	.csid_csi2_rx_lane3_misr_addr                 = 0x15c,

	.csid_csi2_rx_total_pkts_rcvd_addr            = 0x160,

	.csid_csi2_rx_stats_ecc_addr                  = 0x164,

	.csid_csi2_rx_total_crc_err_addr              = 0x168,

	.csid_csi2_rx_de_scramble_type3_cfg0_addr     = 0x170,

	.csid_csi2_rx_de_scramble_type3_cfg1_addr     = 0x174,

	.csid_csi2_rx_de_scramble_type2_cfg0_addr     = 0x178,

	.csid_csi2_rx_de_scramble_type2_cfg1_addr     = 0x17c,

	.csid_csi2_rx_de_scramble_type1_cfg0_addr     = 0x180,

	.csid_csi2_rx_de_scramble_type1_cfg1_addr     = 0x184,

	.csid_csi2_rx_de_scramble_type0_cfg0_addr     = 0x188,

	.csid_csi2_rx_de_scramble_type0_cfg1_addr     = 0x18c,



	.csi2_rst_srb_all                             = 0x3FFF,

	.csi2_rst_done_shift_val                      = 27,

	.csi2_irq_mask_all                            = 0xFFFFFFF,

	.csi2_misr_enable_shift_val                   = 6,

	.csi2_vc_mode_shift_val                       = 2,

	.csi2_capture_long_pkt_en_shift               = 0,

	.csi2_capture_short_pkt_en_shift              = 1,

	.csi2_capture_cphy_pkt_en_shift               = 2,

	.csi2_capture_long_pkt_dt_shift               = 4,

	.csi2_capture_long_pkt_vc_shift               = 10,

	.csi2_capture_short_pkt_vc_shift              = 15,

	.csi2_capture_cphy_pkt_dt_shift               = 20,

	.csi2_capture_cphy_pkt_vc_shift               = 26,

	.csi2_rx_phy_num_mask                         = 0x7,

};



static struct cam_ife_csid_csi2_tpg_reg_offset

			cam_ife_csid_170_200_tpg_reg_offset = {

	/*CSID TPG control */

	.csid_tpg_ctrl_addr                           = 0x600,

	.csid_tpg_vc_cfg0_addr                        = 0x604,

	.csid_tpg_vc_cfg1_addr                        = 0x608,

	.csid_tpg_lfsr_seed_addr                      = 0x60c,

	.csid_tpg_dt_n_cfg_0_addr                     = 0x610,

	.csid_tpg_dt_n_cfg_1_addr                     = 0x614,

	.csid_tpg_dt_n_cfg_2_addr                     = 0x618,

	.csid_tpg_color_bars_cfg_addr                 = 0x640,

	.csid_tpg_color_box_cfg_addr                  = 0x644,

	.csid_tpg_common_gen_cfg_addr                 = 0x648,

	.csid_tpg_cgen_n_cfg_addr                     = 0x650,

	.csid_tpg_cgen_n_x0_addr                      = 0x654,

	.csid_tpg_cgen_n_x1_addr                      = 0x658,

	.csid_tpg_cgen_n_x2_addr                      = 0x65c,

	.csid_tpg_cgen_n_xy_addr                      = 0x660,

	.csid_tpg_cgen_n_y1_addr                      = 0x664,

	.csid_tpg_cgen_n_y2_addr                      = 0x668,



	/* configurations */

	.tpg_dtn_cfg_offset                           = 0xc,

	.tpg_cgen_cfg_offset                          = 0x20,

	.tpg_cpas_ife_reg_offset                      = 0x28,

};



static struct cam_ife_csid_common_reg_offset

			cam_ife_csid_170_200_cmn_reg_offset = {

	.csid_hw_version_addr                         = 0x0,

	.csid_cfg0_addr                               = 0x4,

	.csid_ctrl_addr                               = 0x8,

	.csid_reset_addr                              = 0xc,

	.csid_rst_strobes_addr                        = 0x10,



	.csid_test_bus_ctrl_addr                      = 0x14,

	.csid_top_irq_status_addr                     = 0x70,

	.csid_top_irq_mask_addr                       = 0x74,

	.csid_top_irq_clear_addr                      = 0x78,

	.csid_top_irq_set_addr                        = 0x7c,

	.csid_irq_cmd_addr                            = 0x80,



	/*configurations */

	.major_version                                = 1,

	.minor_version                                = 7,

	.version_incr                                 = 0,

	.num_rdis                                     = 3,

	.num_pix                                      = 1,

	.num_ppp                                      = 1,

	.csid_reg_rst_stb                             = 1,

	.csid_rst_stb                                 = 0x1e,

	.csid_rst_stb_sw_all                          = 0x1f,

	.path_rst_stb_all                             = 0x7f,

	.path_rst_done_shift_val                      = 1,

	.path_en_shift_val                            = 31,

	.packing_fmt_shift_val                        = 30,

	.dt_id_shift_val                              = 27,

	.vc_shift_val                                 = 22,

	.dt_shift_val                                 = 16,

	.fmt_shift_val                                = 12,

	.plain_fmt_shit_val                           = 10,

	.crop_v_en_shift_val                          = 6,

	.crop_h_en_shift_val                          = 5,

	.crop_shift                                   = 16,

	.ipp_irq_mask_all                             = 0xFFFF,

	.rdi_irq_mask_all                             = 0xFFFF,

	.ppp_irq_mask_all                             = 0xFFFF,

	.measure_en_hbi_vbi_cnt_mask                  = 0xC,

	.format_measure_en_val                        = 1,

};



static struct cam_ife_csid_reg_offset cam_ife_csid_170_200_reg_offset = {

	.cmn_reg          = &cam_ife_csid_170_200_cmn_reg_offset,

	.csi2_reg         = &cam_ife_csid_170_200_csi2_reg_offset,

	.ipp_reg          = &cam_ife_csid_170_200_ipp_reg_offset,

	.ppp_reg          = &cam_ife_csid_170_200_ppp_reg_offset,

	.rdi_reg = {

		&cam_ife_csid_170_200_rdi_0_reg_offset,

		&cam_ife_csid_170_200_rdi_1_reg_offset,

		&cam_ife_csid_170_200_rdi_2_reg_offset,

		NULL,

		},

	.tpg_reg = &cam_ife_csid_170_200_tpg_reg_offset,

};



#endif /*_CAM_IFE_CSID_170_200_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid17x.c

+11 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 */





#include <linux/module.h>

#include "cam_ife_csid_core.h"

#include "cam_ife_csid170.h"

#include "cam_ife_csid170_200.h"

#include "cam_ife_csid175.h"

#include "cam_ife_csid175_200.h"

#include "cam_ife_csid480.h"
@@ -22,6 +23,11 @@ static struct cam_ife_csid_hw_info cam_ife_csid170_hw_info = { 
	.hw_dts_version = CAM_CSID_VERSION_V170,

};



static struct cam_ife_csid_hw_info cam_ife_csid170_200_hw_info = {

	.csid_reg = &cam_ife_csid_170_200_reg_offset,

	.hw_dts_version = CAM_CSID_VERSION_V170,

};



static struct cam_ife_csid_hw_info cam_ife_csid175_hw_info = {

	.csid_reg = &cam_ife_csid_175_reg_offset,

	.hw_dts_version = CAM_CSID_VERSION_V175,
@@ -42,6 +48,10 @@ static const struct of_device_id cam_ife_csid17x_dt_match[] = { 
		.compatible = "qcom,csid170",

		.data = &cam_ife_csid170_hw_info,

	},

	{

		.compatible = "qcom,csid170_200",

		.data = &cam_ife_csid170_200_hw_info,

	},

	{

		.compatible = "qcom,csid175",

		.data = &cam_ife_csid175_hw_info,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c

+92 −71
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 */



#include <linux/iopoll.h>
@@ -763,6 +763,7 @@ int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw, 
	case CAM_CPAS_TITAN_170_V100:

	case CAM_CPAS_TITAN_170_V110:

	case CAM_CPAS_TITAN_170_V120:

	case CAM_CPAS_TITAN_170_V200:

		if (cid_reserv->in_port->res_type == CAM_ISP_IFE_IN_RES_PHY_3 &&

			csid_hw->hw_intf->hw_idx != 2) {

			rc = -EINVAL;
@@ -770,7 +771,10 @@ int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw, 
		}

		break;

	case CAM_CPAS_TITAN_480_V100:

		if (cid_reserv->in_port->cust_node == 1) {



		if (cid_reserv->in_port->cust_node != 1)

			break;



		if (cid_reserv->in_port->usage_type == 1) {

			CAM_ERR(CAM_ISP, "Dual IFE is not supported");

			rc = -EINVAL;
@@ -782,7 +786,6 @@ int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw, 
			rc = -EINVAL;

			goto end;

		}

		}

		break;

	default:

		break;
@@ -796,30 +799,33 @@ int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw, 
			goto end;

		}



		if (cid_reserv->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) {

			if (csid_hw->csi2_rx_cfg.lane_cfg !=

		if ((cid_reserv->in_port->res_type !=

			CAM_ISP_IFE_IN_RES_TPG) &&

			(csid_hw->csi2_rx_cfg.lane_cfg !=

			cid_reserv->in_port->lane_cfg  ||

			csid_hw->csi2_rx_cfg.lane_type !=

			cid_reserv->in_port->lane_type ||

			csid_hw->csi2_rx_cfg.lane_num !=

				cid_reserv->in_port->lane_num) {

			cid_reserv->in_port->lane_num)) {



			rc = -EINVAL;

			goto end;

		}

		} else {

			if (csid_hw->tpg_cfg.in_format !=

		if ((cid_reserv->in_port->res_type ==

			CAM_ISP_IFE_IN_RES_TPG) &&

			(csid_hw->tpg_cfg.in_format !=

			cid_reserv->in_port->format     ||

			csid_hw->tpg_cfg.width !=

			cid_reserv->in_port->left_width ||

			csid_hw->tpg_cfg.height !=

			cid_reserv->in_port->height     ||

			csid_hw->tpg_cfg.test_pattern !=

				cid_reserv->in_port->test_pattern) {

			cid_reserv->in_port->test_pattern)) {



			rc = -EINVAL;

			goto end;

		}

	}

	}



	switch (cid_reserv->res_id) {

	case CAM_IFE_PIX_PATH_RES_IPP:
@@ -902,7 +908,17 @@ int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw, 
		csid_hw->csi2_rx_cfg.lane_num =

			cid_reserv->in_port->lane_num;



		if (cid_reserv->in_port->res_type == CAM_ISP_IFE_IN_RES_TPG) {

		if (cid_reserv->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) {

			csid_hw->csi2_rx_cfg.phy_sel =

				(cid_reserv->in_port->res_type & 0xFF) - 1;

			csid_hw->csi2_reserve_cnt++;

			CAM_DBG(CAM_ISP, "CSID:%d CID:%d acquired",

				csid_hw->hw_intf->hw_idx,

				cid_reserv->node_res->res_id);

			goto end;

		}



		/* Below code is executed only for TPG in_res type */

		csid_hw->csi2_rx_cfg.phy_sel = 0;

		if (cid_reserv->in_port->format >

		    CAM_FORMAT_MIPI_RAW_16) {
@@ -931,10 +947,6 @@ int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw, 
			csid_hw->tpg_cfg.height);



		cid_data->tpg_set = 1;

		} else {

			csid_hw->csi2_rx_cfg.phy_sel =

				(cid_reserv->in_port->res_type & 0xFF) - 1;

		}

	}



	csid_hw->csi2_reserve_cnt++;
@@ -1971,17 +1983,26 @@ static int cam_ife_csid_enable_pxl_path( 


	CAM_DBG(CAM_ISP, "Enable %s path", (is_ipp) ? "IPP" : "PPP");





	/* Set master or slave path */

	if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER)

	if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER) {

		/*Set halt mode as master */

		if (pxl_reg->halt_master_sel_en)

			val = pxl_reg->halt_sel_internal_master_val << 4 |

				CSID_HALT_MODE_MASTER << 2;

		else

			val = CSID_HALT_MODE_MASTER << 2;

	else if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE)

	} else if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) {

		/*Set halt mode as slave and set master idx */

		val = path_data->master_idx  << 4 | CSID_HALT_MODE_SLAVE << 2;

		if (pxl_reg->halt_master_sel_en)

			val = CSID_HALT_MODE_SLAVE << 2;

		else

			val = path_data->master_idx  << 4 |

				CSID_HALT_MODE_SLAVE << 2;

	} else {

		/* Default is internal halt mode */

		val = 0;



	}

	/*

	 * Resume at frame boundary if Master or No Sync.

	 * Slave will get resume command from Master.

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h

+3 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _CAM_IFE_CSID_HW_H_
@@ -139,6 +139,8 @@ struct cam_ife_csid_pxl_reg_offset { 
	uint32_t quad_cfa_bin_en_shift_val;

	uint32_t ccif_violation_en;

	uint32_t overflow_ctrl_en;

	uint32_t halt_master_sel_en;

	uint32_t halt_sel_internal_master_val;

};



struct cam_ife_csid_rdi_reg_offset {