Merge "msm: kgsl: Add a property to query gpu speed bin" (93b3d48f) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/gpu/msm/adreno-gpulist.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -480,7 +480,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = {
		.patchid = ANY_ID,
		.features = ADRENO_64BIT \| ADRENO_CONTENT_PROTECTION \|
		ADRENO_IOCOHERENT \| ADRENO_PREEMPTION \| ADRENO_GPMU \|
		ADRENO_IFPC,
		ADRENO_IFPC \| ADRENO_PERFCTRL_RETAIN,
		.sqefw_name = "a630_sqe.fw",
		.zap_name = "a608_zap",
		.gpudev = &adreno_a6xx_gpudev,

drivers/gpu/msm/adreno.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -2423,6 +2423,9 @@ static int adreno_prop_u32(struct kgsl_device *device,
		else if (type == KGSL_PROP_DEVICE_BITNESS)
		val = adreno_support_64bit(adreno_dev) ? 48 : 32;

		else if (type == KGSL_PROP_SPEED_BIN)
		val = adreno_dev->speed_bin;

		return copy_prop(value, count, &val, sizeof(val));
		}

		@@ -2444,6 +2447,7 @@ static struct {
		[KGSL_PROP_MIN_ACCESS_LENGTH] = { .func = adreno_prop_u32 },
		[KGSL_PROP_UBWC_MODE] = { .func = adreno_prop_u32 },
		[KGSL_PROP_DEVICE_BITNESS] = { .func = adreno_prop_u32 },
		[KGSL_PROP_SPEED_BIN] = { .func = adreno_prop_u32 },
		};

		static int adreno_getproperty(struct kgsl_device *device,

drivers/gpu/msm/adreno.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -115,6 +115,8 @@
		#define ADRENO_MIN_VOLT BIT(15)
		/* The core supports IO-coherent memory */
		#define ADRENO_IOCOHERENT BIT(16)
		/* To retain RBBM perfcntl enable setting in IFPC */
		#define ADRENO_PERFCTRL_RETAIN BIT(17)
		/*
		* The GMU supports Adaptive Clock Distribution (ACD)
		* for droop mitigation

drivers/gpu/msm/adreno_a6xx.c

+42 −3

Original line number	Diff line number	Diff line
		@@ -525,6 +525,10 @@ static struct reg_list_pair a615_pwrup_reglist[] = {
		{ A6XX_UCHE_GBIF_GX_CONFIG, 0x0 },
		};

		static struct reg_list_pair a6xx_ifpc_perfctr_reglist[] = {
		{ A6XX_RBBM_PERFCTR_CNTL, 0x0 },
		};

		static void _update_always_on_regs(struct adreno_device *adreno_dev)
		{
		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
		@@ -790,7 +794,7 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev)
		+ sizeof(a6xx_ifpc_pwrup_reglist), a6xx_pwrup_reglist,
		sizeof(a6xx_pwrup_reglist));

		if (adreno_is_a615_family(adreno_dev) \|\| adreno_is_a608(adreno_dev)) {
		if (adreno_is_a615_family(adreno_dev)) {
		for (i = 0; i < ARRAY_SIZE(a615_pwrup_reglist); i++) {
		r = &a615_pwrup_reglist[i];
		kgsl_regread(KGSL_DEVICE(adreno_dev),
		@@ -804,6 +808,22 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev)

		lock->list_length += sizeof(a615_pwrup_reglist) >> 2;
		}

		if (ADRENO_FEATURE(adreno_dev, ADRENO_PERFCTRL_RETAIN)) {
		for (i = 0; i < ARRAY_SIZE(a6xx_ifpc_perfctr_reglist); i++) {
		r = &a6xx_ifpc_perfctr_reglist[i];
		kgsl_regread(KGSL_DEVICE(adreno_dev),
		r->offset, &r->val);
		}

		memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock)
		+ sizeof(a6xx_ifpc_pwrup_reglist)
		+ sizeof(a6xx_pwrup_reglist),
		a6xx_ifpc_perfctr_reglist,
		sizeof(a6xx_ifpc_perfctr_reglist));

		lock->list_length += sizeof(a6xx_ifpc_perfctr_reglist) >> 2;
		}
		}

		/*
		@@ -2977,9 +2997,28 @@ static int a6xx_perfcounter_update(struct adreno_device *adreno_dev,
		for (i = 0; i < lock->list_length >> 1; i++)
		if (reg_pair[i].offset == reg->select)
		break;
		/*
		* If the perfcounter selct register is not present overwrite last entry
		* with new entry and add RBBM perf counter enable at the end.
		*/
		if (ADRENO_FEATURE(adreno_dev, ADRENO_PERFCTRL_RETAIN) &&
		(i == lock->list_length >> 1)) {
		reg_pair[i-1].offset = reg->select;
		reg_pair[i-1].val = reg->countable;

		/* Enable perf counter after performance counter selections */
		reg_pair[i].offset = A6XX_RBBM_PERFCTR_CNTL;
		reg_pair[i].val = 1;

		} else {
		/*
		* If perf counter select register is already present in reglist
		* just update list without adding the RBBM perfcontrol enable.
		*/
		reg_pair[i].offset = reg->select;
		reg_pair[i].val = reg->countable;
		}

		if (i == lock->list_length >> 1)
		lock->list_length += 2;

drivers/gpu/msm/adreno_a6xx_gmu.c

+6 −1

Original line number	Diff line number	Diff line
		@@ -203,7 +203,12 @@ static int _load_gmu_rpmh_ucode(struct kgsl_device *device)
		_regwrite(cfg, PDC_GPU_TCS3_CMD0_DATA, 2);
		_regwrite(cfg, PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET, 0x10108);
		_regwrite(cfg, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET, 0x30000);

		if (adreno_is_a618(adreno_dev))
		_regwrite(cfg, PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET, 0x2);
		else
		_regwrite(cfg, PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET, 0x3);

		_regwrite(cfg, PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);

		if ((ADRENO_GPUREV(adreno_dev) >= 640) \|\| adreno_is_a618(adreno_dev))