Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 938361e7 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

drm/i915/cnp: Panel Power sequence changes for CNP PCH. 



Panel Power sequences for CNP is similar to Broxton,
but with only one sequencer.

Main difference from SPT is that PP_DIVISOR was removed
and power cycle delay has been moved to PP_CONTROL.

v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4]
    as on Broxton. (Found by DK)

v3: Improve commit message. (By DK)

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarClinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1496434004-29812-6-git-send-email-rodrigo.vivi@intel.com
parent 3d02352c

drivers/gpu/drm/i915/intel_dp.c

+6 −6
Original line number Diff line number Diff line
@@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv, 
	regs->pp_stat = PP_STATUS(pps_idx);

	regs->pp_on = PP_ON_DELAYS(pps_idx);

	regs->pp_off = PP_OFF_DELAYS(pps_idx);

	if (!IS_GEN9_LP(dev_priv))

	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))

		regs->pp_div = PP_DIVISOR(pps_idx);

}
@@ -5124,7 +5124,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, 


	pp_on = I915_READ(regs.pp_on);

	pp_off = I915_READ(regs.pp_off);

	if (!IS_GEN9_LP(dev_priv)) {

	if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {

		I915_WRITE(regs.pp_ctrl, pp_ctl);

		pp_div = I915_READ(regs.pp_div);

	}
@@ -5142,7 +5142,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, 
	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>

		   PANEL_POWER_DOWN_DELAY_SHIFT;



	if (IS_GEN9_LP(dev_priv)) {

	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {

		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>

			BXT_POWER_CYCLE_DELAY_SHIFT;

		if (tmp > 0)
@@ -5299,7 +5299,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);

	/* Compute the divisor for the pp clock, simply match the Bspec

	 * formula. */

	if (IS_GEN9_LP(dev_priv)) {

	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {

		pp_div = I915_READ(regs.pp_ctrl);

		pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;

		pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
@@ -5325,7 +5325,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 


	I915_WRITE(regs.pp_on, pp_on);

	I915_WRITE(regs.pp_off, pp_off);

	if (IS_GEN9_LP(dev_priv))

	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))

		I915_WRITE(regs.pp_ctrl, pp_div);

	else

		I915_WRITE(regs.pp_div, pp_div);
@@ -5333,7 +5333,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 
	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",

		      I915_READ(regs.pp_on),

		      I915_READ(regs.pp_off),

		      IS_GEN9_LP(dev_priv) ?

		      (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?

		      (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :

		      I915_READ(regs.pp_div));

}