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Commit 936c663a authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'perf/x86' into perf/core, because it's ready 



Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents 072e5a1c 50f16a8b

arch/arm/kernel/hw_breakpoint.c

+1 −1
Original line number Diff line number Diff line
@@ -648,7 +648,7 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) 
		 * Per-cpu breakpoints are not supported by our stepping

		 * mechanism.

		 */

		if (!bp->hw.bp_target)

		if (!bp->hw.target)

			return -EINVAL;



		/*

arch/arm64/kernel/hw_breakpoint.c

+1 −1
Original line number Diff line number Diff line
@@ -527,7 +527,7 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) 
	 * Disallow per-task kernel breakpoints since these would

	 * complicate the stepping code.

	 */

	if (info->ctrl.privilege == AARCH64_BREAKPOINT_EL1 && bp->hw.bp_target)

	if (info->ctrl.privilege == AARCH64_BREAKPOINT_EL1 && bp->hw.target)

		return -EINVAL;



	return 0;

arch/x86/include/asm/cpufeature.h

+8 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
#include <asm/disabled-features.h>

#endif



#define NCAPINTS	11	/* N 32-bit words worth of info */

#define NCAPINTS	13	/* N 32-bit words worth of info */

#define NBUGINTS	1	/* N 32-bit bug flags */



/*
@@ -226,6 +226,7 @@ 
#define X86_FEATURE_ERMS	( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */

#define X86_FEATURE_INVPCID	( 9*32+10) /* Invalidate Processor Context ID */

#define X86_FEATURE_RTM		( 9*32+11) /* Restricted Transactional Memory */

#define X86_FEATURE_CQM		( 9*32+12) /* Cache QoS Monitoring */

#define X86_FEATURE_MPX		( 9*32+14) /* Memory Protection Extension */

#define X86_FEATURE_AVX512F	( 9*32+16) /* AVX-512 Foundation */

#define X86_FEATURE_RDSEED	( 9*32+18) /* The RDSEED instruction */
@@ -242,6 +243,12 @@ 
#define X86_FEATURE_XGETBV1	(10*32+ 2) /* XGETBV with ECX = 1 */

#define X86_FEATURE_XSAVES	(10*32+ 3) /* XSAVES/XRSTORS */



/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */

#define X86_FEATURE_CQM_LLC	(11*32+ 1) /* LLC QoS if 1 */



/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */

#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */



/*

 * BUG word(s)

 */

arch/x86/include/asm/processor.h

+3 −0
Original line number Diff line number Diff line
@@ -109,6 +109,9 @@ struct cpuinfo_x86 { 
	/* in KB - valid for CPUS which support this call: */

	int			x86_cache_size;

	int			x86_cache_alignment;	/* In bytes */

	/* Cache QoS architectural values: */

	int			x86_cache_max_rmid;	/* max index */

	int			x86_cache_occ_scale;	/* scale to bytes */

	int			x86_power;

	unsigned long		loops_per_jiffy;

	/* cpuid returned max cores value: */

arch/x86/kernel/cpu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ obj-$(CONFIG_CPU_SUP_AMD) += perf_event_amd_iommu.o 
endif

obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_p6.o perf_event_knc.o perf_event_p4.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_intel_rapl.o

obj-$(CONFIG_CPU_SUP_INTEL)		+= perf_event_intel_rapl.o perf_event_intel_cqm.o



obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE)	+= perf_event_intel_uncore.o \

					   perf_event_intel_uncore_snb.o \