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Commit 931474c4 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-radeon-next' of /ssd/git/drm-radeon-next into drm-core-next 

* 'drm-radeon-next' of /ssd/git/drm-radeon-next: (32 commits)
  drivers/gpu/drm/radeon/atom.c: fix warning
  drm/radeon/kms: bump kms version number
  drm/radeon/kms: properly set num banks for fusion asics
  drm/radeon/kms/atom: move dig phy init out of modesetting
  drm/radeon/kms/cayman: fix typo in register mask
  drm/radeon/kms: fix typo in spread spectrum code
  drm/radeon/kms: fix tile_config value reported to userspace on cayman.
  drm/radeon/kms: fix incorrect comparison in cayman setup code.
  drm/radeon/kms: add wait idle ioctl for eg->cayman
  drm/radeon/cayman: setup hdp to invalidate and flush when asked
  drm/radeon/evergreen/btc/fusion: setup hdp to invalidate and flush when asked
  agp/uninorth: Fix lockups with radeon KMS and >1x.
  drm/radeon/kms: the SS_Id field in the LCD table if for LVDS only
  drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices
  drm/radeon/kms: fixup eDP connector handling
  drm/radeon/kms: bail early for eDP in hotplug callback
  drm/radeon/kms: simplify hotplug handler logic
  drm/radeon/kms: rewrite DP handling
  drm/radeon/kms/atom: add support for setting DP panel mode
  drm/radeon/kms: atombios.h updates for DP panel mode
  ...
parents 351fc4d6 2ec8a5fe

drivers/char/agp/uninorth-agp.c

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ static void uninorth_tlbflush(struct agp_memory *mem) 
			       ctrl | UNI_N_CFG_GART_INVAL);

	pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl);



	if (uninorth_rev <= 0x30) {

	if (!mem && uninorth_rev <= 0x30) {

		pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,

				       ctrl | UNI_N_CFG_GART_2xRESET);

		pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,

drivers/gpu/drm/radeon/atom.c

+2 −2
Original line number Diff line number Diff line
@@ -652,12 +652,12 @@ static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg) 


static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)

{

	uint8_t count = U8((*ptr)++);

	unsigned count = U8((*ptr)++);

	SDEBUG("   count: %d\n", count);

	if (arg == ATOM_UNIT_MICROSEC)

		udelay(count);

	else

		schedule_timeout_uninterruptible(msecs_to_jiffies(count));

		msleep(count);

}



static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)

drivers/gpu/drm/radeon/atombios.h

+20 −2
Original line number Diff line number Diff line
@@ -726,6 +726,7 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 
#define ATOM_ENCODER_CMD_DP_VIDEO_ON                  0x0d

#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS    0x0e

#define ATOM_ENCODER_CMD_SETUP                        0x0f

#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE             0x10



// ucStatus

#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE    0x10
@@ -765,6 +766,7 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 
  USHORT usPixelClock;      // in 10KHz; for bios convenient

  ATOM_DIG_ENCODER_CONFIG_V3 acConfig;

  UCHAR ucAction;                              

  union {

    UCHAR ucEncoderMode;

                            // =0: DP   encoder      

                            // =1: LVDS encoder
@@ -772,6 +774,11 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 
                            // =3: HDMI encoder

                            // =4: SDVO encoder

                            // =5: DP audio

    UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE

	                    // =0:     external DP

	                    // =1:     internal DP2

	                    // =0x11:  internal DP1 for NutMeg/Travis DP translator

  };

  UCHAR ucLaneNum;          // how many lanes to enable

  UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP

  UCHAR ucReserved;
@@ -816,6 +823,7 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 
  UCHAR ucConfig;

  };

  UCHAR ucAction;                              

  union {

    UCHAR ucEncoderMode;

                            // =0: DP   encoder      

                            // =1: LVDS encoder
@@ -823,6 +831,11 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 
                            // =3: HDMI encoder

                            // =4: SDVO encoder

                            // =5: DP audio

    UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE

	                    // =0:     external DP

	                    // =1:     internal DP2

	                    // =0x11:  internal DP1 for NutMeg/Travis DP translator

  };

  UCHAR ucLaneNum;          // how many lanes to enable

  UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP

  UCHAR ucHPD_ID;           // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
@@ -836,6 +849,11 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 
#define PANEL_12BIT_PER_COLOR                            0x04

#define PANEL_16BIT_PER_COLOR                            0x05



//define ucPanelMode

#define DP_PANEL_MODE_EXTERNAL_DP_MODE                   0x00

#define DP_PANEL_MODE_INTERNAL_DP2_MODE                  0x01

#define DP_PANEL_MODE_INTERNAL_DP1_MODE                  0x11



/****************************************************************************/	

// Structures used by UNIPHYTransmitterControlTable

//                    LVTMATransmitterControlTable

drivers/gpu/drm/radeon/atombios_crtc.c

+88 −44
Original line number Diff line number Diff line
@@ -420,7 +420,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc, 


	if (ASIC_IS_DCE5(rdev)) {

		args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);

		args.v3.ucSpreadSpectrumType = ss->type;

		args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;

		switch (pll_id) {

		case ATOM_PPLL1:

			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
@@ -440,10 +440,12 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc, 
		case ATOM_PPLL_INVALID:

			return;

		}

		args.v2.ucEnable = enable;

		args.v3.ucEnable = enable;

		if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))

			args.v3.ucEnable = ATOM_DISABLE;

	} else if (ASIC_IS_DCE4(rdev)) {

		args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);

		args.v2.ucSpreadSpectrumType = ss->type;

		args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;

		switch (pll_id) {

		case ATOM_PPLL1:

			args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
@@ -464,32 +466,36 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc, 
			return;

		}

		args.v2.ucEnable = enable;

		if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))

			args.v2.ucEnable = ATOM_DISABLE;

	} else if (ASIC_IS_DCE3(rdev)) {

		args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);

		args.v1.ucSpreadSpectrumType = ss->type;

		args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;

		args.v1.ucSpreadSpectrumStep = ss->step;

		args.v1.ucSpreadSpectrumDelay = ss->delay;

		args.v1.ucSpreadSpectrumRange = ss->range;

		args.v1.ucPpll = pll_id;

		args.v1.ucEnable = enable;

	} else if (ASIC_IS_AVIVO(rdev)) {

		if (enable == ATOM_DISABLE) {

		if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||

		    (ss->type & ATOM_EXTERNAL_SS_MASK)) {

			atombios_disable_ss(crtc);

			return;

		}

		args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);

		args.lvds_ss_2.ucSpreadSpectrumType = ss->type;

		args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;

		args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;

		args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;

		args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;

		args.lvds_ss_2.ucEnable = enable;

	} else {

		if (enable == ATOM_DISABLE) {

		if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||

		    (ss->type & ATOM_EXTERNAL_SS_MASK)) {

			atombios_disable_ss(crtc);

			return;

		}

		args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);

		args.lvds_ss.ucSpreadSpectrumType = ss->type;

		args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;

		args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;

		args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;

		args.lvds_ss.ucEnable = enable;
@@ -512,6 +518,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 
	struct radeon_device *rdev = dev->dev_private;

	struct drm_encoder *encoder = NULL;

	struct radeon_encoder *radeon_encoder = NULL;

	struct drm_connector *connector = NULL;

	u32 adjusted_clock = mode->clock;

	int encoder_mode = 0;

	u32 dp_clock = mode->clock;
@@ -546,9 +553,12 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {

		if (encoder->crtc == crtc) {

			radeon_encoder = to_radeon_encoder(encoder);

			connector = radeon_get_connector_for_encoder(encoder);

			if (connector)

				bpc = connector->display_info.bpc;

			encoder_mode = atombios_get_encoder_mode(encoder);

			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {

				struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);

			if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||

			    radeon_encoder_is_dp_bridge(encoder)) {

				if (connector) {

					struct radeon_connector *radeon_connector = to_radeon_connector(connector);

					struct radeon_connector_atom_dig *dig_connector =
@@ -612,7 +622,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 
				args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);

				args.v1.ucTransmitterID = radeon_encoder->encoder_id;

				args.v1.ucEncodeMode = encoder_mode;

				if (ss_enabled)

				if (ss_enabled && ss->percentage)

					args.v1.ucConfig |=

						ADJUST_DISPLAY_CONFIG_SS_ENABLE;
@@ -625,10 +635,11 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, 
				args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;

				args.v3.sInput.ucEncodeMode = encoder_mode;

				args.v3.sInput.ucDispPllConfig = 0;

				if (ss_enabled)

				if (ss_enabled && ss->percentage)

					args.v3.sInput.ucDispPllConfig |=

						DISPPLL_CONFIG_SS_ENABLE;

				if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {

				if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) ||

				    radeon_encoder_is_dp_bridge(encoder)) {

					struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

					if (encoder_mode == ATOM_ENCODER_MODE_DP) {

						args.v3.sInput.ucDispPllConfig |=
@@ -754,7 +765,10 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc, 
				      u32 ref_div,

				      u32 fb_div,

				      u32 frac_fb_div,

				      u32 post_div)

				      u32 post_div,

				      int bpc,

				      bool ss_enabled,

				      struct radeon_atom_ss *ss)

{

	struct drm_device *dev = crtc->dev;

	struct radeon_device *rdev = dev->dev_private;
@@ -801,6 +815,8 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc, 
			args.v3.ucPostDiv = post_div;

			args.v3.ucPpll = pll_id;

			args.v3.ucMiscInfo = (pll_id << 2);

			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))

				args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;

			args.v3.ucTransmitterId = encoder_id;

			args.v3.ucEncoderMode = encoder_mode;

			break;
@@ -812,6 +828,17 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc, 
			args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);

			args.v5.ucPostDiv = post_div;

			args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */

			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))

				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;

			switch (bpc) {

			case 8:

			default:

				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;

				break;

			case 10:

				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;

				break;

			}

			args.v5.ucTransmitterID = encoder_id;

			args.v5.ucEncoderMode = encoder_mode;

			args.v5.ucPpll = pll_id;
@@ -824,6 +851,23 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc, 
			args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);

			args.v6.ucPostDiv = post_div;

			args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */

			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))

				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;

			switch (bpc) {

			case 8:

			default:

				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;

				break;

			case 10:

				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;

				break;

			case 12:

				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;

				break;

			case 16:

				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;

				break;

			}

			args.v6.ucTransmitterID = encoder_id;

			args.v6.ucEncoderMode = encoder_mode;

			args.v6.ucPpll = pll_id;
@@ -855,6 +899,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode 
	int encoder_mode = 0;

	struct radeon_atom_ss ss;

	bool ss_enabled = false;

	int bpc = 8;



	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {

		if (encoder->crtc == crtc) {
@@ -891,22 +936,12 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode 
		struct radeon_connector_atom_dig *dig_connector =

			radeon_connector->con_priv;

		int dp_clock;

		bpc = connector->display_info.bpc;



		switch (encoder_mode) {

		case ATOM_ENCODER_MODE_DP:

			/* DP/eDP */

			dp_clock = dig_connector->dp_clock / 10;

			if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {

				if (ASIC_IS_DCE4(rdev))

					ss_enabled =

						radeon_atombios_get_asic_ss_info(rdev, &ss,

										 dig->lcd_ss_id,

										 dp_clock);

				else

					ss_enabled =

						radeon_atombios_get_ppll_ss_info(rdev, &ss,

										 dig->lcd_ss_id);

			} else {

			if (ASIC_IS_DCE4(rdev))

				ss_enabled =

					radeon_atombios_get_asic_ss_info(rdev, &ss,
@@ -926,7 +961,6 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode 
						radeon_atombios_get_ppll_ss_info(rdev, &ss,

										 ATOM_DP_SS_ID1);

			}

			}

			break;

		case ATOM_ENCODER_MODE_LVDS:

			if (ASIC_IS_DCE4(rdev))
@@ -974,7 +1008,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode 


	atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,

				  encoder_mode, radeon_encoder->encoder_id, mode->clock,

				  ref_div, fb_div, frac_fb_div, post_div);

				  ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);



	if (ss_enabled) {

		/* calculate ss amount and step size */
@@ -982,7 +1016,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode 
			u32 step_size;

			u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;

			ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;

			ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &

			ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &

				ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;

			if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)

				step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
@@ -1395,11 +1429,19 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
	uint32_t pll_in_use = 0;



	if (ASIC_IS_DCE4(rdev)) {

		/* if crtc is driving DP and we have an ext clock, use that */

		list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {

			if (test_encoder->crtc && (test_encoder->crtc == crtc)) {

				/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,

				 * depending on the asic:

				 * DCE4: PPLL or ext clock

				 * DCE5: DCPLL or ext clock

				 *

				 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip

				 * PPLL/DCPLL programming and only program the DP DTO for the

				 * crtc virtual pixel clock.

				 */

				if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {

					if (rdev->clock.dp_extclk)

					if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)

						return ATOM_PPLL_INVALID;

				}

			}
@@ -1515,6 +1557,8 @@ static void atombios_crtc_commit(struct drm_crtc *crtc) 
static void atombios_crtc_disable(struct drm_crtc *crtc)

{

	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

	struct radeon_atom_ss ss;



	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);



	switch (radeon_crtc->pll_id) {
@@ -1522,7 +1566,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc) 
	case ATOM_PPLL2:

		/* disable the ppll */

		atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,

					  0, 0, ATOM_DISABLE, 0, 0, 0, 0);

					  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);

		break;

	default:

		break;

drivers/gpu/drm/radeon/atombios_dp.c

+579 −467

File changed.

Preview size limit exceeded, changes collapsed.