Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 9293267a authored by Carol L Soto's avatar Carol L Soto Committed by David S. Miller
Browse files

net/mlx4_core: Capping number of requested MSIXs to MAX_MSIX 



We currently manage IRQs in pool_bm which is a bit field
of MAX_MSIX bits. Thus, allocating more than MAX_MSIX
interrupts can't be managed in pool_bm.
Fixing this by capping number of requested MSIXs to
MAX_MSIX.

Signed-off-by: default avatarMatan Barak <matanb@mellanox.com>
Signed-off-by: default avatarCarol L Soto <clsoto@linux.vnet.ibm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b22fbf22

drivers/net/ethernet/mellanox/mlx4/main.c

+9 −1
Original line number Diff line number Diff line
@@ -2669,9 +2669,14 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev) 


	if (msi_x) {

		int nreq = dev->caps.num_ports * num_online_cpus() + 1;

		bool shared_ports = false;



		nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,

			     nreq);

		if (nreq > MAX_MSIX) {

			nreq = MAX_MSIX;

			shared_ports = true;

		}



		entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);

		if (!entries)
@@ -2694,6 +2699,9 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev) 
		bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,

			    dev->caps.num_ports);



		if (MLX4_IS_LEGACY_EQ_MODE(dev->caps))

			shared_ports = true;



		for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {

			if (i == MLX4_EQ_ASYNC)

				continue;
@@ -2701,7 +2709,7 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev) 
			priv->eq_table.eq[i].irq =

				entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;



			if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {

			if (shared_ports) {

				bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,

					    dev->caps.num_ports);

				/* We don't set affinity hint when there