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Commit 9249dee6 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Will Deacon
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dt-bindings: Document devicetree binding for ARM DSU PMU 



This patch documents the devicetree bindings for ARM DSU PMU.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: devicetree@vger.kernel.org
Cc: frowand.list@gmail.com
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 66582787

Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt

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* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)



ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores

with a shared L3 memory system, control logic and external interfaces to

form a multicore cluster. The PMU enables to gather various statistics on

the operations of the DSU. The PMU provides independent 32bit counters that

can count any of the supported events, along with a 64bit cycle counter.

The PMU is accessed via CPU system registers and has no MMIO component.



** DSU PMU required properties:



- compatible	: should be one of :



		"arm,dsu-pmu"



- interrupts	: Exactly 1 SPI must be listed.



- cpus		: List of phandles for the CPUs connected to this DSU instance.





** Example:



dsu-pmu-0 {

	compatible = "arm,dsu-pmu";

	interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;

	cpus = <&cpu_0>, <&cpu_1>;

};