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Commit 9181dba6 authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/vg20:Enable the 2nd instance for uvd 



For Vega20, set num of uvd instance to 2, to enble 2nd instance.
The IB test build-in registers need update for vega20 2nd instance.

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3b17c622

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

+16 −14
Original line number Diff line number Diff line
@@ -72,11 +72,12 @@ 
#define FIRMWARE_VEGA12		"amdgpu/vega12_uvd.bin"

#define FIRMWARE_VEGA20		"amdgpu/vega20_uvd.bin"



#define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00)

#define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00)

#define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00)

#define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00)

#define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00)

/* These are common relative offsets for all asics, from uvd_7_0_offset.h,  */

#define UVD_GPCOM_VCPU_CMD		0x03c3

#define UVD_GPCOM_VCPU_DATA0	0x03c4

#define UVD_GPCOM_VCPU_DATA1	0x03c5

#define UVD_NO_OP				0x03ff

#define UVD_BASE_SI				0x3800



/**

 * amdgpu_uvd_cs_ctx - Command submission parser context
@@ -990,6 +991,8 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 
	uint64_t addr;

	long r;

	int i;

	unsigned offset_idx = 0;

	unsigned offset[3] = { UVD_BASE_SI, 0, 0 };



	amdgpu_bo_kunmap(bo);

	amdgpu_bo_unpin(bo);
@@ -1009,17 +1012,16 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 
		goto err;



	if (adev->asic_type >= CHIP_VEGA10) {

		data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0);

		data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0);

		data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0);

		data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0);

	} else {

		data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);

		data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);

		data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);

		data[3] = PACKET0(mmUVD_NO_OP, 0);

		offset_idx = 1 + ring->me;

		offset[1] = adev->reg_offset[UVD_HWIP][0][1];

		offset[2] = adev->reg_offset[UVD_HWIP][1][1];

	}



	data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);

	data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);

	data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);

	data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);



	ib = &job->ibs[0];

	addr = amdgpu_bo_gpu_offset(bo);

	ib->ptr[0] = data[0];

drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

+6 −1
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ 
#include "mmhub/mmhub_1_0_offset.h"

#include "mmhub/mmhub_1_0_sh_mask.h"



#define UVD7_MAX_HW_INSTANCES_VEGA20			2



static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);

static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);

static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -370,6 +372,9 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 
static int uvd_v7_0_early_init(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (adev->asic_type == CHIP_VEGA20)

		adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20;

	else

		adev->uvd.num_uvd_inst = 1;



	if (amdgpu_sriov_vf(adev))