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Commit 913a6b3d authored by Christophe Leroy's avatar Christophe Leroy Committed by Scott Wood
Browse files

powerpc/8xx: Save r3 all the time in DTLB miss handler 



We are spending between 40 and 160 cycles with a mean of 65 cycles in
the DTLB handling routine (measured with mftbl) so make it more
simple althought it adds one instruction.
With this modification, we get three registers available at all time,
which will help with following patch.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarScott Wood <oss@buserror.net>
parent 3b5eb41b

arch/powerpc/kernel/head_8xx.S

+4 −9
Original line number Diff line number Diff line
@@ -385,23 +385,20 @@ InstructionTLBMiss: 


	. = 0x1200

DataStoreTLBMiss:

#ifdef CONFIG_8xx_CPU6

	mtspr	SPRN_SPRG_SCRATCH2, r3

#endif

	EXCEPTION_PROLOG_0

	mfcr	r10

	mfcr	r3



	/* If we are faulting a kernel address, we have to use the

	 * kernel page tables.

	 */

	mfspr	r11, SPRN_MD_EPN

	IS_KERNEL(r11, r11)

	mfspr	r10, SPRN_MD_EPN

	IS_KERNEL(r11, r10)

	mfspr	r11, SPRN_M_TW	/* Get level 1 table */

	BRANCH_UNLESS_KERNEL(3f)

	lis	r11, (swapper_pg_dir-PAGE_OFFSET)@ha

3:

	mtcr	r10

	mfspr	r10, SPRN_MD_EPN

	mtcr	r3



	/* Insert level 1 index */

	rlwimi	r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
@@ -453,9 +450,7 @@ DataStoreTLBMiss: 
	MTSPR_CPU6(SPRN_MD_RPN, r10, r3)	/* Update TLB entry */



	/* Restore registers */

#ifdef CONFIG_8xx_CPU6

	mfspr	r3, SPRN_SPRG_SCRATCH2

#endif

	mtspr	SPRN_DAR, r11	/* Tag DAR */

	EXCEPTION_EPILOG_0

	rfi