Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8fd3ffa9 authored by Thierry Reding's avatar Thierry Reding
Browse files

drm/tegra: dc: Rename register for consistency 



The horizontal pulse enable bits are named H_PULSE{0,1,2}_ENABLE in the
TRM. Modify the driver to use the same naming for consistency.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 791ddb1e

drivers/gpu/drm/tegra/dc.h

+3 −3
Original line number Original line Diff line number Diff line
@@ -119,9 +119,9 @@ 
#define DC_COM_CRC_CHECKSUM_LATCHED		0x329

#define DC_COM_CRC_CHECKSUM_LATCHED		0x329





#define DC_DISP_DISP_SIGNAL_OPTIONS0		0x400

#define DC_DISP_DISP_SIGNAL_OPTIONS0		0x400

#define H_PULSE_0_ENABLE (1 <<  8)

#define H_PULSE0_ENABLE (1 <<  8)

#define H_PULSE_1_ENABLE (1 << 10)

#define H_PULSE1_ENABLE (1 << 10)

#define H_PULSE_2_ENABLE (1 << 12)

#define H_PULSE2_ENABLE (1 << 12)





#define DC_DISP_DISP_SIGNAL_OPTIONS1		0x401

#define DC_DISP_DISP_SIGNAL_OPTIONS1		0x401

drivers/gpu/drm/tegra/hdmi.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -878,7 +878,7 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder, 
	/* video_preamble uses h_pulse2 */

	/* video_preamble uses h_pulse2 */

	pulse_start = 1 + h_sync_width + h_back_porch - 10;

	pulse_start = 1 + h_sync_width + h_back_porch - 10;





	tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);

	tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);





	value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |

	value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |

		PULSE_LAST_END_A;

		PULSE_LAST_END_A;