drm/i915: VLV_DDL is VLV only and needs an offset

/* drain latency register values*/

#define DRAIN_LATENCY_PRECISION_32	32

#define DRAIN_LATENCY_PRECISION_16	16

#define VLV_DDL1			0x70050

#define VLV_DDL1			(VLV_DISPLAY_BASE + 0x70050)

#define DDL_CURSORA_PRECISION_32	(1<<31)

#define DDL_CURSORA_PRECISION_16	(0<<31)

#define DDL_CURSORA_SHIFT		24

#define DDL_PLANEA_PRECISION_32		(1<<7)

#define DDL_PLANEA_PRECISION_16		(0<<7)

#define VLV_DDL2			0x70054

#define VLV_DDL2			(VLV_DISPLAY_BASE + 0x70054)

#define DDL_CURSORB_PRECISION_32	(1<<31)

#define DDL_CURSORB_PRECISION_16	(0<<31)

#define DDL_CURSORB_SHIFT		24