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Commit 8f6a9042 authored Oct 09, 2017 by Vaibhav Jain Committed by Michael Ellerman Oct 10, 2017

cxl: Rename register PSL9_FIR2 to PSL9_FIR_MASK



PSL9 doesn't have a FIR2 register as was the case with PSL8. However
currently the register definitions in 'cxl.h' have a definition for
PSL9_FIR2 that actually points to PSL9_FIR_MASK register in the P1
area at offset 0x308.

So this patch renames the def PSL9_FIR2 to PSL9_FIR_MASK and updates
the references in the code to point to the new identifier. It also
removes the code to dump contents of FIR2 (FIR_MASK actually) in
cxl_native_irq_dump_regs_psl9().

Fixes: f24be42a ("cxl: Add psl9 specific code")
Reported-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

parent 56328743

drivers/misc/cxl/cxl.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -104,7 +104,7 @@ static const cxl_p1_reg_t CXL_XSL9_INV = {0x0110};
	static const cxl_p1_reg_t CXL_XSL9_DEF = {0x0140};		static const cxl_p1_reg_t CXL_XSL9_DEF = {0x0140};
	static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};		static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};
	static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};		static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};
	static const cxl_p1_reg_t CXL_PSL9_FIR2 = {0x0308};		static const cxl_p1_reg_t CXL_PSL9_FIR_MASK = {0x0308};
	static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};		static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};
	static const cxl_p1_reg_t CXL_PSL9_DEBUG = {0x0320};		static const cxl_p1_reg_t CXL_PSL9_DEBUG = {0x0320};
	static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};		static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};

drivers/misc/cxl/debugfs.c

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -62,7 +62,8 @@ static struct dentry debugfs_create_io_x64(const char name, umode_t mode,
	void cxl_debugfs_add_adapter_regs_psl9(struct cxl adapter, struct dentry dir)		void cxl_debugfs_add_adapter_regs_psl9(struct cxl adapter, struct dentry dir)
	{		{
	debugfs_create_io_x64("fir1", S_IRUSR, dir, _cxl_p1_addr(adapter, CXL_PSL9_FIR1));		debugfs_create_io_x64("fir1", S_IRUSR, dir, _cxl_p1_addr(adapter, CXL_PSL9_FIR1));
	debugfs_create_io_x64("fir2", S_IRUSR, dir, _cxl_p1_addr(adapter, CXL_PSL9_FIR2));		debugfs_create_io_x64("fir_mask", 0400, dir,
			_cxl_p1_addr(adapter, CXL_PSL9_FIR_MASK));
	debugfs_create_io_x64("fir_cntl", S_IRUSR, dir, _cxl_p1_addr(adapter, CXL_PSL9_FIR_CNTL));		debugfs_create_io_x64("fir_cntl", S_IRUSR, dir, _cxl_p1_addr(adapter, CXL_PSL9_FIR_CNTL));
	debugfs_create_io_x64("trace", S_IRUSR \| S_IWUSR, dir, _cxl_p1_addr(adapter, CXL_PSL9_TRACECFG));		debugfs_create_io_x64("trace", S_IRUSR \| S_IWUSR, dir, _cxl_p1_addr(adapter, CXL_PSL9_TRACECFG));
	}		}

drivers/misc/cxl/native.c

+1 −3

Original line number	Original line	Diff line number	Diff line
	@@ -1085,13 +1085,11 @@ static int native_get_irq_info(struct cxl_afu afu, struct cxl_irq_info info)

	void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx)		void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx)
	{		{
	u64 fir1, fir2, serr;		u64 fir1, serr;

	fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR1);		fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR1);
	fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL9_FIR2);

	dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);		dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1);
	dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2);
	if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {		if (ctx->afu->adapter->native->sl_ops->register_serr_irq) {
	serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);		serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An);
	cxl_afu_decode_psl_serr(ctx->afu, serr);		cxl_afu_decode_psl_serr(ctx->afu, serr);