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Commit 8f1d169f authored by Joonyoung Shim's avatar Joonyoung Shim Committed by Greg Kroah-Hartman
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ARM: EXYNOS4: Add usb host phy control



EXYNOS4 has 2 phys for usb host and usb device. This patch supports to
control usb host phy of EXYNOS4.

Signed-off-by: default avatarJoonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 3e112662
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+2 −0
Original line number Diff line number Diff line
@@ -54,3 +54,5 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)	+= setup-keypad.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI)	+= setup-sdhci.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o

obj-$(CONFIG_USB_SUPPORT)		+= usb-phy.o
+6 −1
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@@ -97,7 +97,12 @@ static struct map_desc exynos4_iodesc[] __initdata = {
		.pfn		= __phys_to_pfn(EXYNOS4_PA_SROMC),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	},
	}, {
		.virtual	= (unsigned long)S5P_VA_USB_HSPHY,
		.pfn		= __phys_to_pfn(EXYNOS4_PA_HSPHY),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}
};

static void exynos4_idle(void)
+1 −0
Original line number Diff line number Diff line
@@ -102,6 +102,7 @@
#define EXYNOS4_PA_SROMC		0x12570000

#define EXYNOS4_PA_EHCI			0x12580000
#define EXYNOS4_PA_HSPHY		0x125B0000

#define EXYNOS4_PA_UART			0x13800000

+3 −0
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@@ -33,6 +33,9 @@
#define S5P_EINT_WAKEUP_MASK			S5P_PMUREG(0x0604)
#define S5P_WAKEUP_MASK				S5P_PMUREG(0x0608)

#define S5P_USBHOST_PHY_CONTROL			S5P_PMUREG(0x0708)
#define S5P_USBHOST_PHY_ENABLE			(1 << 0)

#define S5P_MIPI_DPHY_CONTROL(n)		S5P_PMUREG(0x0710 + (n) * 4)
#define S5P_MIPI_DPHY_ENABLE			(1 << 0)
#define S5P_MIPI_DPHY_SRESETN			(1 << 1)
+64 −0
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/*
 * Copyright (C) 2011 Samsung Electronics Co.Ltd
 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef __PLAT_S5P_REGS_USB_PHY_H
#define __PLAT_S5P_REGS_USB_PHY_H

#define EXYNOS4_HSOTG_PHYREG(x)		((x) + S5P_VA_USB_HSPHY)

#define EXYNOS4_PHYPWR			EXYNOS4_HSOTG_PHYREG(0x00)
#define PHY1_HSIC_NORMAL_MASK		(0xf << 9)
#define PHY1_HSIC1_SLEEP		(1 << 12)
#define PHY1_HSIC1_FORCE_SUSPEND	(1 << 11)
#define PHY1_HSIC0_SLEEP		(1 << 10)
#define PHY1_HSIC0_FORCE_SUSPEND	(1 << 9)

#define PHY1_STD_NORMAL_MASK		(0x7 << 6)
#define PHY1_STD_SLEEP			(1 << 8)
#define PHY1_STD_ANALOG_POWERDOWN	(1 << 7)
#define PHY1_STD_FORCE_SUSPEND		(1 << 6)

#define PHY0_NORMAL_MASK		(0x39 << 0)
#define PHY0_SLEEP			(1 << 5)
#define PHY0_OTG_DISABLE		(1 << 4)
#define PHY0_ANALOG_POWERDOWN		(1 << 3)
#define PHY0_FORCE_SUSPEND		(1 << 0)

#define EXYNOS4_PHYCLK			EXYNOS4_HSOTG_PHYREG(0x04)
#define PHY1_COMMON_ON_N		(1 << 7)
#define PHY0_COMMON_ON_N		(1 << 4)
#define PHY0_ID_PULLUP			(1 << 2)
#define CLKSEL_MASK			(0x3 << 0)
#define CLKSEL_SHIFT			(0)
#define CLKSEL_48M			(0x0 << 0)
#define CLKSEL_12M			(0x2 << 0)
#define CLKSEL_24M			(0x3 << 0)

#define EXYNOS4_RSTCON			EXYNOS4_HSOTG_PHYREG(0x08)
#define HOST_LINK_PORT_SWRST_MASK	(0xf << 6)
#define HOST_LINK_PORT2_SWRST		(1 << 9)
#define HOST_LINK_PORT1_SWRST		(1 << 8)
#define HOST_LINK_PORT0_SWRST		(1 << 7)
#define HOST_LINK_ALL_SWRST		(1 << 6)

#define PHY1_SWRST_MASK			(0x7 << 3)
#define PHY1_HSIC_SWRST			(1 << 5)
#define PHY1_STD_SWRST			(1 << 4)
#define PHY1_ALL_SWRST			(1 << 3)

#define PHY0_SWRST_MASK			(0x7 << 0)
#define PHY0_PHYLINK_SWRST		(1 << 2)
#define PHY0_HLINK_SWRST		(1 << 1)
#define PHY0_SWRST			(1 << 0)

#define EXYNOS4_PHY1CON			EXYNOS4_HSOTG_PHYREG(0x34)
#define FPENABLEN			(1 << 0)

#endif /* __PLAT_S5P_REGS_USB_PHY_H */
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