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Commit 8ee218b3 authored by Baochu Xu's avatar Baochu Xu
Browse files

ARM: dts: qcom: Enable audio for rb5 

Enable audio for rb5.
Remove WCD9385 codec for rb5.
Remove mic bias widget from record path.
Add 2 WSA8815 smart PA for rb5.
Modify WSA enable pin for rb5.

Change-Id: I6fcf434c05c46a1b294b9b39fc1cd524c5ba2c1f
parent 96e5bad9

qcom/kona-iot-rb5-audio.dtsi

0 → 100644
+300 −0
Original line number Diff line number Diff line 


&spkr_2_sd_n_sleep {

	mux {

		pins = "gpio130";

	};



	config {

		pins = "gpio130";

	};

};



&spkr_2_sd_n_active {

	mux {

		pins = "gpio130";

	};



	config {

		pins = "gpio130";

	};

};





&bolero {

	qcom,num-macros = <4>;

	bolero-clk-rsc-mngr {

		compatible = "qcom,bolero-clk-rsc-mngr";

		qcom,fs-gen-sequence = <0x3000 0x1>,

					<0x3004 0x1>, <0x3080 0x2>;

	qcom,rx_mclk_mode_muxsel = <0x033240D8>;

	qcom,wsa_mclk_mode_muxsel = <0x033220D8>;

	qcom,va_mclk_mode_muxsel = <0x033A0000>;

	clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",

		 "wsa_core_clk", "wsa_npl_clk", "va_core_clk", "va_npl_clk";

	clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,

		<&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,

		<&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,

		<&clock_audio_va_1 0>, <&clock_audio_va_2 0>;

	};



	tx_macro: tx-macro@3220000 {

		compatible = "qcom,tx-macro";

		reg = <0x3220000 0x0>;

		clock-names = "tx_core_clk", "tx_npl_clk";

		clocks = <&clock_audio_tx_1 0>,

			 <&clock_audio_tx_2 0>;

		qcom,tx-swr-gpios = <&tx_swr_gpios>;

		qcom,tx-dmic-sample-rate = <2400000>;

		swr2: tx_swr_master {

			status = "disabled";

			compatible = "qcom,swr-mstr";

			#address-cells = <2>;

			#size-cells = <0>;

			clock-names = "lpass_core_hw_vote",

					"lpass_audio_hw_vote";

			clocks = <&lpass_core_hw_vote 0>,

					<&lpass_audio_hw_vote 0>;

			qcom,swr_master_id = <3>;

			qcom,mipi-sdw-block-packing-mode = <1>;

			swrm-io-base = <0x3230000 0x0>;

			interrupts-extended =

				<&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 109 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "swr_master_irq", "swr_wake_irq";

			qcom,swr-wakeup-required = <1>;

			qcom,swr-num-ports = <5>;

			qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,

				<2 ADC1 0x1>, <2 ADC2 0x2>,

				<3 ADC3 0x1>, <3 ADC4 0x2>,

				<4 DMIC0 0x1>, <4 DMIC1 0x2>,

				<4 DMIC2 0x4>, <4 DMIC3 0x8>,

				<5 DMIC4 0x1>, <5 DMIC5 0x2>,

				<5 DMIC6 0x4>, <5 DMIC7 0x8>;

			qcom,swr-num-dev = <1>;

			qcom,swr-clock-stop-mode0 = <1>;

			qcom,swr-mstr-irq-wakeup-capable = <1>;

			wcd938x_tx_slave: wcd938x-tx-slave {

				compatible = "qcom,wcd938x-slave";

				reg = <0x0D 0x01170223>;

			};

		};

	};



	rx_macro: rx-macro@3200000 {

		compatible = "qcom,rx-macro";

		reg = <0x3200000 0x0>;

		clock-names = "rx_core_clk", "rx_npl_clk";

		clocks = <&clock_audio_rx_1 0>,

			 <&clock_audio_rx_2 0>;

		qcom,rx-swr-gpios = <&rx_swr_gpios>;

		qcom,rx_mclk_mode_muxsel = <0x033240D8>;

		qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;

		qcom,default-clk-id = <TX_CORE_CLK>;

		swr1: rx_swr_master {

			status = "disabled";

			compatible = "qcom,swr-mstr";

			#address-cells = <2>;

			#size-cells = <0>;

			clock-names = "lpass_core_hw_vote",

					"lpass_audio_hw_vote";

			clocks = <&lpass_core_hw_vote 0>,

					<&lpass_audio_hw_vote 0>;

			qcom,swr_master_id = <2>;

			qcom,mipi-sdw-block-packing-mode = <1>;

			swrm-io-base = <0x3210000 0x0>;

			interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "swr_master_irq";

			qcom,swr-num-ports = <5>;

			qcom,swr-port-mapping = <1 HPH_L 0x1>,

				<1 HPH_R 0x2>, <2 CLSH 0x1>,

				<3 COMP_L 0x1>, <3 COMP_R 0x2>,

				<4 LO 0x1>, <5 DSD_L 0x1>,

				<5 DSD_R 0x2>;

			qcom,swr-num-dev = <1>;

			qcom,swr-clock-stop-mode0 = <1>;

			wcd938x_rx_slave: wcd938x-rx-slave {

				compatible = "qcom,wcd938x-slave";

				reg = <0x0D 0x01170224>;

			};

		};

	};



	wsa_macro: wsa-macro@3240000 {

		compatible = "qcom,wsa-macro";

		reg = <0x3240000 0x0>;

		clock-names = "wsa_core_clk", "wsa_npl_clk";

		clocks = <&clock_audio_wsa_1 0>,

			 <&clock_audio_wsa_2 0>;

		qcom,wsa-swr-gpios = <&wsa_swr_gpios>;

		qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;

		qcom,default-clk-id = <TX_CORE_CLK>;

		swr0: wsa_swr_master {

			compatible = "qcom,swr-mstr";

			#address-cells = <2>;

			#size-cells = <0>;

			clock-names = "lpass_core_hw_vote",

					"lpass_audio_hw_vote";

			clocks = <&lpass_core_hw_vote 0>,

					<&lpass_audio_hw_vote 0>;

			qcom,swr_master_id = <1>;

			qcom,mipi-sdw-block-packing-mode = <0>;

			swrm-io-base = <0x3250000 0x0>;

			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "swr_master_irq";

			qcom,swr-num-ports = <8>;

			qcom,swr-port-mapping = <1 SPKR_L 0x1>,

				<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,

				<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,

				<6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,

				<8 SPKR_R_VI 0x3>;

			qcom,swr-num-dev = <2>;

			wsa881x_0211: wsa881x@20170211 {

				compatible = "qcom,wsa881x";

				reg = <0x10 0x20170211>;

				qcom,spkr-sd-n-node = <&wsa_spkr_en2>;

				qcom,bolero-handle = <&bolero>;

			};



			wsa881x_0212: wsa881x@20170212 {

				compatible = "qcom,wsa881x";

				reg = <0x10 0x20170212>;

				qcom,spkr-sd-n-node = <&wsa_spkr_en2>;

				qcom,bolero-handle = <&bolero>;

			};



			wsa881x_0213: wsa881x@21170213 {

				compatible = "qcom,wsa881x";

				reg = <0x10 0x21170213>;

				qcom,spkr-sd-n-node = <&wsa_spkr_en2>;

				qcom,bolero-handle = <&bolero>;

			};



			wsa881x_0214: wsa881x@21170214 {

				compatible = "qcom,wsa881x";

				reg = <0x10 0x21170214>;

				qcom,spkr-sd-n-node = <&wsa_spkr_en2>;

				qcom,bolero-handle = <&bolero>;

			};

		};



	};



	wcd938x_codec: wcd938x-codec {

		status = "disabled";

		compatible = "qcom,wcd938x-codec";

		qcom,split-codec = <1>;

		qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,

			<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,

			<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,

			<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,

			<4 DSD_R 0x2 0 DSD_R>;

		qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,

			<0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>,

			<1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>,

			<2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>,

			<2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>,

			<3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>,

			<3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>;



		qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;

		qcom,rx-slave = <&wcd938x_rx_slave>;

		qcom,tx-slave = <&wcd938x_tx_slave>;



		cdc-vdd-rxtx-supply = <&S4A>;

		qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;

		qcom,cdc-vdd-rxtx-current = <30000>;



		cdc-vddio-supply = <&S4A>;

		qcom,cdc-vddio-voltage = <1800000 1800000>;

		qcom,cdc-vddio-current = <30000>;



		cdc-vdd-buck-supply = <&S4A>;

		qcom,cdc-vdd-buck-voltage = <1800000 1800000>;

		qcom,cdc-vdd-buck-current = <650000>;



		cdc-vdd-mic-bias-supply = <&BOB>;

		qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;

		qcom,cdc-vdd-mic-bias-current = <30000>;



		qcom,cdc-micbias1-mv = <1800>;

		qcom,cdc-micbias2-mv = <1800>;

		qcom,cdc-micbias3-mv = <1800>;

		qcom,cdc-micbias4-mv = <1800>;



		qcom,cdc-static-supplies = "cdc-vdd-rxtx",

					   "cdc-vddio",

					   "cdc-vdd-buck",

					   "cdc-vdd-mic-bias";

	};



};



&kona_snd {

	qcom,model = "kona-qrd-snd-card";

	qcom,audio-routing =

		"TX DMIC0", "Digital Mic0",

		"TX DMIC1", "Digital Mic1",

		"TX DMIC2", "Digital Mic2",

		"TX DMIC3", "Digital Mic3",

		"TX DMIC4", "Digital Mic4",

		"TX DMIC5", "Digital Mic5",

		"IN1_HPHL", "HPHL_OUT",

		"IN2_HPHR", "HPHR_OUT",

		"IN3_AUX", "AUX_OUT",

		"TX SWR_ADC0", "ADC1_OUTPUT",

		"TX SWR_ADC1", "ADC2_OUTPUT",

		"TX SWR_ADC2", "ADC3_OUTPUT",

		"TX SWR_ADC3", "ADC4_OUTPUT",

		"TX SWR_DMIC0", "DMIC1_OUTPUT",

		"TX SWR_DMIC1", "DMIC2_OUTPUT",

		"TX SWR_DMIC2", "DMIC3_OUTPUT",

		"TX SWR_DMIC3", "DMIC4_OUTPUT",

		"TX SWR_DMIC4", "DMIC5_OUTPUT",

		"TX SWR_DMIC5", "DMIC6_OUTPUT",

		"TX SWR_DMIC6", "DMIC7_OUTPUT",

		"TX SWR_DMIC7", "DMIC8_OUTPUT",

		"WSA SRC0_INP", "SRC0",

		"WSA_TX DEC0_INP", "TX DEC0 MUX",

		"WSA_TX DEC1_INP", "TX DEC1 MUX",

		"RX_TX DEC0_INP", "TX DEC0 MUX",

		"RX_TX DEC1_INP", "TX DEC1 MUX",

		"RX_TX DEC2_INP", "TX DEC2 MUX",

		"RX_TX DEC3_INP", "TX DEC3 MUX",

		"SpkrRight IN", "WSA_SPK2 OUT",

		"VA_AIF1 CAP", "VA_SWR_CLK",

		"VA_AIF2 CAP", "VA_SWR_CLK",

		"VA_AIF3 CAP", "VA_SWR_CLK",

		"VA DMIC0", "Digital Mic0",

		"VA DMIC1", "Digital Mic1",

		"VA DMIC2", "Digital Mic2",

		"VA DMIC3", "Digital Mic3",

		"VA DMIC4", "Digital Mic4",

		"VA DMIC5", "Digital Mic5",

		"VA SWR_ADC1", "VA_SWR_CLK",

		"VA SWR_MIC0", "VA_SWR_CLK",

		"VA SWR_MIC1", "VA_SWR_CLK",

		"VA SWR_MIC2", "VA_SWR_CLK",

		"VA SWR_MIC3", "VA_SWR_CLK",

		"VA SWR_MIC4", "VA_SWR_CLK",

		"VA SWR_MIC5", "VA_SWR_CLK",

		"VA SWR_MIC6", "VA_SWR_CLK",

		"VA SWR_MIC7", "VA_SWR_CLK",

		"VA SWR_MIC0", "DMIC1_OUTPUT",

		"VA SWR_MIC1", "DMIC2_OUTPUT",

		"VA SWR_MIC2", "DMIC3_OUTPUT",

		"VA SWR_MIC3", "DMIC4_OUTPUT",

		"VA SWR_MIC4", "DMIC5_OUTPUT",

		"VA SWR_MIC5", "DMIC6_OUTPUT",

		"VA SWR_MIC6", "DMIC7_OUTPUT",

		"VA SWR_MIC7", "DMIC8_OUTPUT",

		"VA SWR_ADC1", "ADC2_OUTPUT";

	qcom,msm-mbhc-usbc-audio-supported = <1>;

	qcom,msm-mbhc-hphl-swh = <0>;

	qcom,msm-mbhc-gnd-swh = <0>;

	qcom,wsa-max-devs = <2>;

	qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,

			<&wsa881x_0213>, <&wsa881x_0214>;

	qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",

				  "SpkrLeft", "SpkrRight";

	qcom,codec-max-aux-devs = <0>;

};

qcom/kona-v2.1-iot-rb5.dtsi

+1 −0
Original line number Diff line number Diff line 
#include "kona-qrd.dtsi"

#include "kona-iot-rb5-audio.dtsi"



&qupv3_se12_2uart {

	status = "okay";