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Commit 8d9d51b6 authored by Thomas Gleixner's avatar Thomas Gleixner
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Merge tag 'irqchip-4.13' of... 

Merge tag 'irqchip-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates for v4.13 from Marc Zyngier

- support for the new Marvell wire-to-MSI bridge
- support for the Aspeed I2C irqchip
- Armada XP370 per-cpu interrupt fixes
- GICv3 ITS ACPI NUMA support
- sunxi-nmi cleanup and updates for new platform support
- various GICv3 ITS cleanups and fixes
- some constifying in various places
parents 6a6544e5 6c31e123

Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt

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@@ -3,8 +3,11 @@ Allwinner Sunxi NMI Controller 


Required properties:



- compatible : should be "allwinner,sun7i-a20-sc-nmi" or

  "allwinner,sun6i-a31-sc-nmi" or "allwinner,sun9i-a80-nmi"

- compatible : should be one of the following:

  - "allwinner,sun7i-a20-sc-nmi"

  - "allwinner,sun6i-a31-sc-nmi" (deprecated)

  - "allwinner,sun6i-a31-r-intc"

  - "allwinner,sun9i-a80-nmi"

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt

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Device tree configuration for the I2C Interrupt Controller on the AST24XX and

AST25XX SoCs.



Required Properties:

- #address-cells	: should be 1

- #size-cells 		: should be 1

- #interrupt-cells 	: should be 1

- compatible 		: should be "aspeed,ast2400-i2c-ic"

			  or "aspeed,ast2500-i2c-ic"

- reg			: address start and range of controller

- interrupts		: interrupt number

- interrupt-controller	: denotes that the controller receives and fires

			  new interrupts for child busses



Example:



i2c_ic: interrupt-controller@0 {

	#address-cells = <1>;

	#size-cells = <1>;

	#interrupt-cells = <1>;

	compatible = "aspeed,ast2400-i2c-ic";

	reg = <0x0 0x40>;

	interrupts = <12>;

	interrupt-controller;

};

Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-vic.txt

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Aspeed Vectored Interrupt Controller



These bindings are for the Aspeed AST2400 interrupt controller register layout.

The SoC has an legacy register layout, but this driver does not support that

mode of operation.

These bindings are for the Aspeed interrupt controller. The AST2400 and

AST2500 SoC families include a legacy register layout before a re-designed

layout, but the bindings do not prescribe the use of one or the other.



Required properties:



- compatible : should be "aspeed,ast2400-vic".

- compatible : "aspeed,ast2400-vic"

               "aspeed,ast2500-vic"



- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt

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Marvell GICP Controller

-----------------------



GICP is a Marvell extension of the GIC that allows to trigger GIC SPI

interrupts by doing a memory transaction. It is used by the ICU

located in the Marvell CP110 to turn wired interrupts inside the CP

into GIC SPI interrupts.



Required properties:



- compatible: Must be "marvell,ap806-gicp"



- reg: Must be the address and size of the GICP SPI registers



- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available

  for this GICP



- msi-controller: indicates that this is an MSI controller



Example:



gicp_spi: gicp-spi@3f0040 {

	compatible = "marvell,ap806-gicp";

	reg = <0x3f0040 0x10>;

	marvell,spi-ranges = <64 64>, <288 64>;

	msi-controller;

};

Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt

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Marvell ICU Interrupt Controller

--------------------------------



The Marvell ICU (Interrupt Consolidation Unit) controller is

responsible for collecting all wired-interrupt sources in the CP and

communicating them to the GIC in the AP, the unit translates interrupt

requests on input wires to MSG memory mapped transactions to the GIC.



Required properties:



- compatible: Should be "marvell,cp110-icu"



- reg: Should contain ICU registers location and length.



- #interrupt-cells: Specifies the number of cells needed to encode an

  interrupt source. The value shall be 3.



  The 1st cell is the group type of the ICU interrupt. Possible group

  types are:



   ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure

   ICU_GRP_SR  (0x1) : Shared peripheral interrupt, secure

   ICU_GRP_SEI (0x4) : System error interrupt

   ICU_GRP_REI (0x5) : RAM error interrupt



  The 2nd cell is the index of the interrupt in the ICU unit.



  The 3rd cell is the type of the interrupt. See arm,gic.txt for

  details.



- interrupt-controller: Identifies the node as an interrupt

  controller.



- msi-parent: Should point to the GICP controller, the GIC extension

  that allows to trigger interrupts using MSG memory mapped

  transactions.



Example:



icu: interrupt-controller@1e0000 {

	compatible = "marvell,cp110-icu";

	reg = <0x1e0000 0x10>;

	#interrupt-cells = <3>;

	interrupt-controller;

	msi-parent = <&gicp>;

};



usb3h0: usb3@500000 {

	interrupt-parent = <&icu>;

	interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;

};