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Commit 8d6a35fb authored by Sean Cross's avatar Sean Cross Committed by Bjorn Helgaas
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ARM: imx6q: Add PCIe bits to GPR syscon definition 



PCIe requires additional bits be defined for GPR8 and GPR12.

Signed-off-by: default avatarSean Cross <xobs@kosagi.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 4a10c2ac

include/linux/mfd/syscon/imx6q-iomuxc-gpr.h

+8 −0
Original line number Diff line number Diff line
@@ -241,6 +241,12 @@ 


#define IMX6Q_GPR5_L2_CLK_STOP			BIT(8)



#define IMX6Q_GPR8_TX_SWING_LOW			(0x7f << 25)

#define IMX6Q_GPR8_TX_SWING_FULL		(0x7f << 18)

#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB		(0x3f << 12)

#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB		(0x3f << 6)

#define IMX6Q_GPR8_TX_DEEMPH_GEN1		(0x3f << 0)



#define IMX6Q_GPR9_TZASC2_BYP			BIT(1)

#define IMX6Q_GPR9_TZASC1_BYP			BIT(0)
@@ -273,7 +279,9 @@ 
#define IMX6Q_GPR12_ARMP_AHB_CLK_EN		BIT(26)

#define IMX6Q_GPR12_ARMP_ATB_CLK_EN		BIT(25)

#define IMX6Q_GPR12_ARMP_APB_CLK_EN		BIT(24)

#define IMX6Q_GPR12_DEVICE_TYPE			(0xf << 12)

#define IMX6Q_GPR12_PCIE_CTL_2			BIT(10)

#define IMX6Q_GPR12_LOS_LEVEL			(0x1f << 4)



#define IMX6Q_GPR13_SDMA_STOP_REQ		BIT(30)

#define IMX6Q_GPR13_CAN2_STOP_REQ		BIT(29)