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Commit 8d369bb1 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: fix gtt MC base alignment on rs4xx/rs690/rs740 asics 



The asics in question have the following requirements with regard to
their gart setups:

1. The GART aperture size has to be in the form of 2^X bytes, where X is from 25 to 31
2. The GART aperture MC base has to be aligned to a boundary equal to the size of the
aperture.
3. The GART page table has to be aligned to the boundary equal to the size of the table.
4. The GART page table size is: table_entry_size * (aperture_size / page_size)
5. The GART page table has to be allocated in non-paged, non-cached, contiguous system
memory.

This patch takes care 2.  The rest should already be handled properly.

This fixes a regression noticed by: Torsten Kaiser <just.for.lkml@googlemail.com>

Tested-by: default avatarTorsten Kaiser <just.for.lkml@googlemail.com>
Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 5099fa7f

drivers/gpu/drm/radeon/r100.c

+1 −0
Original line number Diff line number Diff line
@@ -2354,6 +2354,7 @@ void r100_mc_init(struct radeon_device *rdev) 
	if (rdev->flags & RADEON_IS_IGP)

		base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;

	radeon_vram_location(rdev, &rdev->mc, base);

	rdev->mc.gtt_base_align = 0;

	if (!(rdev->flags & RADEON_IS_AGP))

		radeon_gtt_location(rdev, &rdev->mc);

	radeon_update_bandwidth_info(rdev);

drivers/gpu/drm/radeon/r300.c

+1 −0
Original line number Diff line number Diff line
@@ -481,6 +481,7 @@ void r300_mc_init(struct radeon_device *rdev) 
	if (rdev->flags & RADEON_IS_IGP)

		base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;

	radeon_vram_location(rdev, &rdev->mc, base);

	rdev->mc.gtt_base_align = 0;

	if (!(rdev->flags & RADEON_IS_AGP))

		radeon_gtt_location(rdev, &rdev->mc);

	radeon_update_bandwidth_info(rdev);

drivers/gpu/drm/radeon/r520.c

+1 −0
Original line number Diff line number Diff line
@@ -125,6 +125,7 @@ void r520_mc_init(struct radeon_device *rdev) 
	r520_vram_get_type(rdev);

	r100_vram_init_sizes(rdev);

	radeon_vram_location(rdev, &rdev->mc, 0);

	rdev->mc.gtt_base_align = 0;

	if (!(rdev->flags & RADEON_IS_AGP))

		radeon_gtt_location(rdev, &rdev->mc);

	radeon_update_bandwidth_info(rdev);

drivers/gpu/drm/radeon/r600.c

+1 −0
Original line number Diff line number Diff line
@@ -1179,6 +1179,7 @@ void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 
		if (rdev->flags & RADEON_IS_IGP)

			base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;

		radeon_vram_location(rdev, &rdev->mc, base);

		rdev->mc.gtt_base_align = 0;

		radeon_gtt_location(rdev, mc);

	}

}

drivers/gpu/drm/radeon/radeon.h

+1 −0
Original line number Diff line number Diff line
@@ -351,6 +351,7 @@ struct radeon_mc { 
	int			vram_mtrr;

	bool			vram_is_ddr;

	bool			igp_sideport_enabled;

	u64                     gtt_base_align;

};



bool radeon_combios_sideport_present(struct radeon_device *rdev);