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Commit 8c448cad authored by Gabriel Feceoru's avatar Gabriel Feceoru Committed by Daniel Vetter
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drm/i915: Handle PipeC fused off on IVB/HSW/BDW 



Some Gen7/8 production parts may have the Display Pipe C fused off.
In this case, the display hardware will prevent the enable bit in
PIPE_CONF register (for Pipe C) from being set to 1.

Fixed by adjusting pipe_count to reflect this.

v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
    on ivybridge (Ville)
v3: Remove unnecessary MMIO read, correct the description (Damien)
v4: Be more specific in description (Patrick)

Signed-off-by: default avatarGabriel Feceoru <gabriel.feceoru@intel.com>
Reviewed-by: default avatarPatrik Jakobsson <patrik.jakobsson@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1453462125-21519-1-git-send-email-gabriel.feceoru@intel.com
parent da3b891b

drivers/gpu/drm/i915/i915_dma.c

+3 −0
Original line number Diff line number Diff line
@@ -808,6 +808,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev) 
		     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {

			DRM_INFO("Display fused off, disabling\n");

			info->num_pipes = 0;

		} else if (fuse_strap & IVB_PIPE_C_DISABLE) {

			DRM_INFO("PipeC fused off\n");

			info->num_pipes -= 1;

		}

	} else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) {

		u32 dfsm = I915_READ(SKL_DFSM);

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -5949,6 +5949,7 @@ enum skl_disp_power_wells { 
#define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)

#define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)

#define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)

#define  IVB_PIPE_C_DISABLE		(1 << 28)

#define  ILK_HDCP_DISABLE		(1 << 25)

#define  ILK_eDP_A_DISABLE		(1 << 24)

#define  HSW_CDCLK_LIMIT		(1 << 24)