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Commit 8c3a13c8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm 

Pull ARM fixes from Russell King:
 "A set of fixes from various people - Will Deacon gets a prize for
  removing code this time around.  The biggest fix in this lot is
  sorting out the ARM740T mess.  The rest are relatively small fixes."

* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
  ARM: 7699/1: sched_clock: Add more notrace to prevent recursion
  ARM: 7698/1: perf: fix group validation when using enable_on_exec
  ARM: 7697/1: hw_breakpoint: do not use __cpuinitdata for dbg_cpu_pm_nb
  ARM: 7696/1: Fix kexec by setting outer_cache.inv_all for Feroceon
  ARM: 7694/1: ARM, TCM: initialize TCM in paging_init(), instead of setup_arch()
  ARM: 7692/1: iop3xx: move IOP3XX_PERIPHERAL_VIRT_BASE
  ARM: modules: don't export cpu_set_pte_ext when !MMU
  ARM: mm: remove broken condition check for v4 flushing
  ARM: mm: fix numerous hideous errors in proc-arm740.S
  ARM: cache: remove ARMv3 support code
  ARM: tlbflush: remove ARMv3 support
parents 851b3f32 cea15092

arch/arm/include/asm/glue-cache.h

+0 −8
Original line number Diff line number Diff line
@@ -19,14 +19,6 @@ 
#undef _CACHE

#undef MULTI_CACHE



#if defined(CONFIG_CPU_CACHE_V3)

# ifdef _CACHE

#  define MULTI_CACHE 1

# else

#  define _CACHE v3

# endif

#endif



#if defined(CONFIG_CPU_CACHE_V4)

# ifdef _CACHE

#  define MULTI_CACHE 1

arch/arm/include/asm/hardware/iop3xx.h

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ extern int iop3xx_get_init_atu(void); 
 * IOP3XX processor registers

 */

#define IOP3XX_PERIPHERAL_PHYS_BASE	0xffffe000

#define IOP3XX_PERIPHERAL_VIRT_BASE	0xfeffe000

#define IOP3XX_PERIPHERAL_VIRT_BASE	0xfedfe000

#define IOP3XX_PERIPHERAL_SIZE		0x00002000

#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\

					IOP3XX_PERIPHERAL_SIZE - 1)

arch/arm/include/asm/tlbflush.h

+2 −9
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ 


#include <asm/glue.h>



#define TLB_V3_PAGE	(1 << 0)

#define TLB_V4_U_PAGE	(1 << 1)

#define TLB_V4_D_PAGE	(1 << 2)

#define TLB_V4_I_PAGE	(1 << 3)
@@ -22,7 +21,6 @@ 
#define TLB_V6_D_PAGE	(1 << 5)

#define TLB_V6_I_PAGE	(1 << 6)



#define TLB_V3_FULL	(1 << 8)

#define TLB_V4_U_FULL	(1 << 9)

#define TLB_V4_D_FULL	(1 << 10)

#define TLB_V4_I_FULL	(1 << 11)
@@ -52,7 +50,6 @@ 
 *	=============

 *

 *	We have the following to choose from:

 *	  v3    - ARMv3

 *	  v4    - ARMv4 without write buffer

 *	  v4wb  - ARMv4 with write buffer without I TLB flush entry instruction

 *	  v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
@@ -330,7 +327,6 @@ static inline void local_flush_tlb_all(void) 
	if (tlb_flag(TLB_WB))

		dsb();



	tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);

	tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero);

	tlb_op(TLB_V4_D_FULL | TLB_V6_D_FULL, "c8, c6, 0", zero);

	tlb_op(TLB_V4_I_FULL | TLB_V6_I_FULL, "c8, c5, 0", zero);
@@ -351,9 +347,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) 
	if (tlb_flag(TLB_WB))

		dsb();



	if (possible_tlb_flags & (TLB_V3_FULL|TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {

	if (possible_tlb_flags & (TLB_V4_U_FULL|TLB_V4_D_FULL|TLB_V4_I_FULL)) {

		if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {

			tlb_op(TLB_V3_FULL, "c6, c0, 0", zero);

			tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero);

			tlb_op(TLB_V4_D_FULL, "c8, c6, 0", zero);

			tlb_op(TLB_V4_I_FULL, "c8, c5, 0", zero);
@@ -385,9 +380,8 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) 
	if (tlb_flag(TLB_WB))

		dsb();



	if (possible_tlb_flags & (TLB_V3_PAGE|TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&

	if (possible_tlb_flags & (TLB_V4_U_PAGE|TLB_V4_D_PAGE|TLB_V4_I_PAGE|TLB_V4_I_FULL) &&

	    cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {

		tlb_op(TLB_V3_PAGE, "c6, c0, 0", uaddr);

		tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr);

		tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", uaddr);

		tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", uaddr);
@@ -418,7 +412,6 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) 
	if (tlb_flag(TLB_WB))

		dsb();



	tlb_op(TLB_V3_PAGE, "c6, c0, 0", kaddr);

	tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr);

	tlb_op(TLB_V4_D_PAGE, "c8, c6, 1", kaddr);

	tlb_op(TLB_V4_I_PAGE, "c8, c5, 1", kaddr);

arch/arm/kernel/hw_breakpoint.c

+1 −1
Original line number Diff line number Diff line
@@ -1043,7 +1043,7 @@ static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action, 
	return NOTIFY_OK;

}



static struct notifier_block __cpuinitdata dbg_cpu_pm_nb = {

static struct notifier_block dbg_cpu_pm_nb = {

	.notifier_call = dbg_cpu_pm_notify,

};

arch/arm/kernel/perf_event.c

+4 −1
Original line number Diff line number Diff line
@@ -253,7 +253,10 @@ validate_event(struct pmu_hw_events *hw_events, 
	struct arm_pmu *armpmu = to_arm_pmu(event->pmu);

	struct pmu *leader_pmu = event->group_leader->pmu;



	if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)

	if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)

		return 1;



	if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)

		return 1;



	return armpmu->get_event_idx(hw_events, event) >= 0;