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Commit 8bdb65dc authored by Zhi Mao's avatar Zhi Mao Committed by Thierry Reding
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pwm: mediatek: Disable clock on PWM configuration failure 



Make sure to disable the PWM clock if the PWM cannot be configured due
to the clock divider exceeding the maximum value.

While at it, replace the hardcoded maximum clock divider with a defined
constant to improve code readability.

Signed-off-by: default avatarZhi Mao <zhi.mao@mediatek.com>
Acked-by: default avatarJohn Crispin <john@phrozen.org>
Signed-off-by: default avatarThierry Reding <thierry.reding@gmail.com>
parent 62843a61

drivers/pwm/pwm-mediatek.c

+6 −1
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ 
#define PWMDWIDTH		0x2c

#define PWMTHRES		0x30



#define PWM_CLK_DIV_MAX		7



enum {

	MTK_CLK_MAIN = 0,

	MTK_CLK_TOP,
@@ -130,8 +132,11 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 
		clkdiv++;

	}



	if (clkdiv > 7)

	if (clkdiv > PWM_CLK_DIV_MAX) {

		mtk_pwm_clk_disable(chip, pwm);

		dev_err(chip->dev, "period %d not supported\n", period_ns);

		return -EINVAL;

	}



	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);

	mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);