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Commit 8b6e70fc authored by Mark Rutland's avatar Mark Rutland Committed by Will Deacon
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arm64: traps: correctly handle MRS/MSR with XZR 



Currently we hand-roll XZR-safe register handling in
user_cache_maint_handler(), though we forget to do the same in
ctr_read_handler(), and may erroneously write back to the user SP rather
than XZR.

Use the new helpers to handle these cases correctly and consistently.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Fixes: 116c81f4 ("arm64: Work around systems with mismatched cache line sizes")
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 6c23e2ff

arch/arm64/kernel/traps.c

+4 −2
Original line number Diff line number Diff line
@@ -466,7 +466,7 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) 
	int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT;

	int ret = 0;



	address = (rt == 31) ? 0 : regs->regs[rt];

	address = pt_regs_read_reg(regs, rt);



	switch (crm) {

	case ESR_ELx_SYS64_ISS_CRM_DC_CVAU:	/* DC CVAU, gets promoted */
@@ -495,8 +495,10 @@ static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) 
static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)

{

	int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;

	unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);



	pt_regs_write_reg(regs, rt, val);



	regs->regs[rt] = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);

	regs->pc += 4;

}