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Commit 8b3016c4 authored by Chris Wilson's avatar Chris Wilson
Browse files

Merge branch 'drm-intel-fixes' into drm-intel-next

parents 021357ac dd8849c8

drivers/gpu/drm/i915/i915_irq.c

+15 −7
Original line number Diff line number Diff line
@@ -1350,17 +1350,25 @@ void i915_hangcheck_elapsed(unsigned long data) 
		i915_seqno_passed(i915_get_gem_seqno(dev,

				&dev_priv->render_ring),

			i915_get_tail_request(dev)->seqno)) {

		bool missed_wakeup = false;



		dev_priv->hangcheck_count = 0;



		/* Issue a wake-up to catch stuck h/w. */

		if (dev_priv->render_ring.waiting_gem_seqno |

		    dev_priv->bsd_ring.waiting_gem_seqno) {

			DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");

			if (dev_priv->render_ring.waiting_gem_seqno)

		if (dev_priv->render_ring.waiting_gem_seqno &&

		    waitqueue_active(&dev_priv->render_ring.irq_queue)) {

			DRM_WAKEUP(&dev_priv->render_ring.irq_queue);

			if (dev_priv->bsd_ring.waiting_gem_seqno)

			missed_wakeup = true;

		}



		if (dev_priv->bsd_ring.waiting_gem_seqno &&

		    waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {

			DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);

			missed_wakeup = true;

		}



		if (missed_wakeup)

			DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");

		return;

	}

drivers/gpu/drm/i915/i915_reg.h

+8 −0
Original line number Diff line number Diff line
@@ -2215,9 +2215,17 @@ 
#define  WM1_LP_SR_EN		(1<<31)

#define  WM1_LP_LATENCY_SHIFT	24

#define  WM1_LP_LATENCY_MASK	(0x7f<<24)

#define  WM1_LP_FBC_LP1_MASK	(0xf<<20)

#define  WM1_LP_FBC_LP1_SHIFT	20

#define  WM1_LP_SR_MASK		(0x1ff<<8)

#define  WM1_LP_SR_SHIFT	8

#define  WM1_LP_CURSOR_MASK	(0x3f)

#define WM2_LP_ILK		0x4510c

#define  WM2_LP_EN		(1<<31)

#define WM3_LP_ILK		0x45110

#define  WM3_LP_EN		(1<<31)

#define WM1S_LP_ILK		0x45120

#define  WM1S_LP_EN		(1<<31)



/* Memory latency timer register */

#define MLTR_ILK		0x11222

drivers/gpu/drm/i915/intel_display.c

+4 −2
Original line number Diff line number Diff line
@@ -3516,8 +3516,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock, 
		reg_value = I915_READ(WM1_LP_ILK);

		reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |

			       WM1_LP_CURSOR_MASK);

		reg_value |= WM1_LP_SR_EN |

			     (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |

		reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |

			     (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;



		I915_WRITE(WM1_LP_ILK, reg_value);
@@ -5839,6 +5838,9 @@ void intel_init_clock_gating(struct drm_device *dev) 
			I915_WRITE(DISP_ARB_CTL,

					(I915_READ(DISP_ARB_CTL) |

						DISP_FBC_WM_DIS));

		I915_WRITE(WM3_LP_ILK, 0);

		I915_WRITE(WM2_LP_ILK, 0);

		I915_WRITE(WM1_LP_ILK, 0);

		}

		/*

		 * Based on the document from hardware guys the following bits