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Commit 8b0f7e06 authored by Kahola, Mika's avatar Kahola, Mika Committed by Rodrigo Vivi
Browse files

drm/i915: Configure DPLL's for Cannonlake 



DPLL's are defined in DPCLKA_CFGCR0 register (0x6C200). Let's use these
definitions when computing dpll's for ddi ports.

v2: (Rodrigo) Remove register that was defined in another patch with
    fixed name and more bits.

Signed-off-by: default avatarKahola, Mika <mika.kahola@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarAnder Conselvan de Oliveira <conselvan2@gmail.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1497047175-27250-6-git-send-email-rodrigo.vivi@intel.com
parent 555e38d2

drivers/gpu/drm/i915/intel_display.c

+19 −1
Original line number Diff line number Diff line
@@ -8868,6 +8868,22 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc, 
	return 0;

}



static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,

				   enum port port,

				   struct intel_crtc_state *pipe_config)

{

	enum intel_dpll_id id;

	u32 temp;



	temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);

	id = temp >> (port * 2);



	if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))

		return;



	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);

}



static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,

				enum port port,

				struct intel_crtc_state *pipe_config)
@@ -9055,7 +9071,9 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, 


	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;



	if (IS_GEN9_BC(dev_priv))

	if (IS_CANNONLAKE(dev_priv))

		cannonlake_get_ddi_pll(dev_priv, port, pipe_config);

	else if (IS_GEN9_BC(dev_priv))

		skylake_get_ddi_pll(dev_priv, port, pipe_config);

	else if (IS_GEN9_LP(dev_priv))

		bxt_get_ddi_pll(dev_priv, port, pipe_config);