Merge branch 'topic/hda' into for-4.2 (8ab418d3) · Commits · e / devices / android_kernel_oneplus_sm7250

include/sound/hda_register.h

0 → 100644

+152 −0

Original line number	Diff line number	Diff line
		/*
		* HD-audio controller (Azalia) registers and helpers
		*
		* For traditional reasons, we still use azx_ prefix here
		*/

		#ifndef __SOUND_HDA_REGISTER_H
		#define __SOUND_HDA_REGISTER_H

		#include <linux/io.h>
		#include <sound/hdaudio.h>

		#define AZX_REG_GCAP 0x00
		#define AZX_GCAP_64OK (1 << 0) /* 64bit address support */
		#define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */
		#define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */
		#define AZX_GCAP_ISS (15 << 8) /* # of input streams */
		#define AZX_GCAP_OSS (15 << 12) /* # of output streams */
		#define AZX_REG_VMIN 0x02
		#define AZX_REG_VMAJ 0x03
		#define AZX_REG_OUTPAY 0x04
		#define AZX_REG_INPAY 0x06
		#define AZX_REG_GCTL 0x08
		#define AZX_GCTL_RESET (1 << 0) /* controller reset */
		#define AZX_GCTL_FCNTRL (1 << 1) /* flush control */
		#define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
		#define AZX_REG_WAKEEN 0x0c
		#define AZX_REG_STATESTS 0x0e
		#define AZX_REG_GSTS 0x10
		#define AZX_GSTS_FSTS (1 << 1) /* flush status */
		#define AZX_REG_INTCTL 0x20
		#define AZX_REG_INTSTS 0x24
		#define AZX_REG_WALLCLK 0x30 /* 24Mhz source */
		#define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
		#define AZX_REG_SSYNC 0x38
		#define AZX_REG_CORBLBASE 0x40
		#define AZX_REG_CORBUBASE 0x44
		#define AZX_REG_CORBWP 0x48
		#define AZX_REG_CORBRP 0x4a
		#define AZX_CORBRP_RST (1 << 15) /* read pointer reset */
		#define AZX_REG_CORBCTL 0x4c
		#define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */
		#define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
		#define AZX_REG_CORBSTS 0x4d
		#define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */
		#define AZX_REG_CORBSIZE 0x4e

		#define AZX_REG_RIRBLBASE 0x50
		#define AZX_REG_RIRBUBASE 0x54
		#define AZX_REG_RIRBWP 0x58
		#define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */
		#define AZX_REG_RINTCNT 0x5a
		#define AZX_REG_RIRBCTL 0x5c
		#define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
		#define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */
		#define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
		#define AZX_REG_RIRBSTS 0x5d
		#define AZX_RBSTS_IRQ (1 << 0) /* response irq */
		#define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */
		#define AZX_REG_RIRBSIZE 0x5e

		#define AZX_REG_IC 0x60
		#define AZX_REG_IR 0x64
		#define AZX_REG_IRS 0x68
		#define AZX_IRS_VALID (1<<1)
		#define AZX_IRS_BUSY (1<<0)

		#define AZX_REG_DPLBASE 0x70
		#define AZX_REG_DPUBASE 0x74
		#define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */

		/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
		enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };

		/* stream register offsets from stream base */
		#define AZX_REG_SD_CTL 0x00
		#define AZX_REG_SD_STS 0x03
		#define AZX_REG_SD_LPIB 0x04
		#define AZX_REG_SD_CBL 0x08
		#define AZX_REG_SD_LVI 0x0c
		#define AZX_REG_SD_FIFOW 0x0e
		#define AZX_REG_SD_FIFOSIZE 0x10
		#define AZX_REG_SD_FORMAT 0x12
		#define AZX_REG_SD_BDLPL 0x18
		#define AZX_REG_SD_BDLPU 0x1c

		/* PCI space */
		#define AZX_PCIREG_TCSEL 0x44

		/*
		* other constants
		*/

		/* max number of fragments - we may use more if allocating more pages for BDL */
		#define BDL_SIZE 4096
		#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
		#define AZX_MAX_FRAG 32
		/* max buffer size - no h/w limit, you can increase as you like */
		#define AZX_MAX_BUF_SIZE (102410241024)

		/* RIRB int mask: overrun[2], response[0] */
		#define RIRB_INT_RESPONSE 0x01
		#define RIRB_INT_OVERRUN 0x04
		#define RIRB_INT_MASK 0x05

		/* STATESTS int mask: S3,SD2,SD1,SD0 */
		#define STATESTS_INT_MASK ((1 << HDA_MAX_CODECS) - 1)

		/* SD_CTL bits */
		#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
		#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
		#define SD_CTL_STRIPE (3 << 16) /* stripe control */
		#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
		#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
		#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
		#define SD_CTL_STREAM_TAG_SHIFT 20

		/* SD_CTL and SD_STS */
		#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
		#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
		#define SD_INT_COMPLETE 0x04 /* completion interrupt */
		#define SD_INT_MASK (SD_INT_DESC_ERR\|SD_INT_FIFO_ERR\|\
		SD_INT_COMPLETE)

		/* SD_STS */
		#define SD_STS_FIFO_READY 0x20 /* FIFO ready */

		/* INTCTL and INTSTS */
		#define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */
		#define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
		#define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */

		/* below are so far hardcoded - should read registers in future */
		#define AZX_MAX_CORB_ENTRIES 256
		#define AZX_MAX_RIRB_ENTRIES 256

		/*
		* helpers to read the stream position
		*/
		static inline unsigned int
		snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream)
		{
		return snd_hdac_stream_readl(stream, SD_LPIB);
		}

		static inline unsigned int
		snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream)
		{
		return le32_to_cpu(*stream->posbuf);
		}

		#endif /* __SOUND_HDA_REGISTER_H */

include/sound/hdaudio.h

+283 −3

Original line number	Diff line number	Diff line
		@@ -6,12 +6,17 @@
		#define __SOUND_HDAUDIO_H

		#include <linux/device.h>
		#include <linux/interrupt.h>
		#include <linux/timecounter.h>
		#include <sound/core.h>
		#include <sound/memalloc.h>
		#include <sound/hda_verbs.h>

		/* codec node id */
		typedef u16 hda_nid_t;

		struct hdac_bus;
		struct hdac_stream;
		struct hdac_device;
		struct hdac_driver;
		struct hdac_widget_tree;
		@@ -85,6 +90,7 @@ struct hdac_device {
		enum {
		HDA_DEV_CORE,
		HDA_DEV_LEGACY,
		HDA_DEV_ASOC,
		};

		/* direction */
		@@ -118,6 +124,15 @@ int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid,
		hda_nid_t *conn_list, int max_conns);
		int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid,
		hda_nid_t *start_id);
		unsigned int snd_hdac_calc_stream_format(unsigned int rate,
		unsigned int channels,
		unsigned int format,
		unsigned int maxbps,
		unsigned short spdif_ctls);
		int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid,
		u32 ratesp, u64 formatsp, unsigned int *bpsp);
		bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid,
		unsigned int format);

		/**
		* snd_hdac_read_parm - read a codec parameter
		@@ -161,7 +176,7 @@ struct hdac_driver {
		#define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver)

		/*
		* HD-audio bus base driver
		* Bus verb operators
		*/
		struct hdac_bus_ops {
		/* send a single command */
		@@ -171,11 +186,55 @@ struct hdac_bus_ops {
		unsigned int *res);
		};

		/*
		* Lowlevel I/O operators
		*/
		struct hdac_io_ops {
		/* mapped register accesses */
		void (reg_writel)(u32 value, u32 __iomem addr);
		u32 (reg_readl)(u32 __iomem addr);
		void (reg_writew)(u16 value, u16 __iomem addr);
		u16 (reg_readw)(u16 __iomem addr);
		void (reg_writeb)(u8 value, u8 __iomem addr);
		u8 (reg_readb)(u8 __iomem addr);
		/* Allocation ops */
		int (dma_alloc_pages)(struct hdac_bus bus, int type, size_t size,
		struct snd_dma_buffer *buf);
		void (dma_free_pages)(struct hdac_bus bus,
		struct snd_dma_buffer *buf);
		};

		#define HDA_UNSOL_QUEUE_SIZE 64
		#define HDA_MAX_CODECS 8 /* limit by controller side */

		/* HD Audio class code */
		#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403

		/*
		* CORB/RIRB
		*
		* Each CORB entry is 4byte, RIRB is 8byte
		*/
		struct hdac_rb {
		__le32 buf; / virtual address of CORB/RIRB buffer */
		dma_addr_t addr; /* physical address of CORB/RIRB buffer */
		unsigned short rp, wp; /* RIRB read/write pointers */
		int cmds[HDA_MAX_CODECS]; /* number of pending requests */
		u32 res[HDA_MAX_CODECS]; /* last read value */
		};

		/*
		* HD-audio bus base driver
		*/
		struct hdac_bus {
		struct device *dev;
		const struct hdac_bus_ops *ops;
		const struct hdac_io_ops *io_ops;

		/* h/w resources */
		unsigned long addr;
		void __iomem *remap_addr;
		int irq;

		/* codec linked list */
		struct list_head codec_list;
		@@ -189,18 +248,45 @@ struct hdac_bus {
		unsigned int unsol_rp, unsol_wp;
		struct work_struct unsol_work;

		/* bit flags of detected codecs */
		unsigned long codec_mask;

		/* bit flags of powered codecs */
		unsigned long codec_powered;

		/* flags */
		/* CORB/RIRB */
		struct hdac_rb corb;
		struct hdac_rb rirb;
		unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */

		/* CORB/RIRB and position buffers */
		struct snd_dma_buffer rb;
		struct snd_dma_buffer posbuf;

		/* hdac_stream linked list */
		struct list_head stream_list;

		/* operation state */
		bool chip_init:1; /* h/w initialized */

		/* behavior flags */
		bool sync_write:1; /* sync after verb write */
		bool use_posbuf:1; /* use position buffer */
		bool snoop:1; /* enable snooping */
		bool align_bdle_4k:1; /* BDLE align 4K boundary */
		bool reverse_assign:1; /* assign devices in reverse order */
		bool corbrp_self_clear:1; /* CORBRP clears itself after reset */

		int bdl_pos_adj; /* BDL position adjustment */

		/* locks */
		spinlock_t reg_lock;
		struct mutex cmd_mutex;
		};

		int snd_hdac_bus_init(struct hdac_bus bus, struct device dev,
		const struct hdac_bus_ops *ops);
		const struct hdac_bus_ops *ops,
		const struct hdac_io_ops *io_ops);
		void snd_hdac_bus_exit(struct hdac_bus *bus);
		int snd_hdac_bus_exec_verb(struct hdac_bus *bus, unsigned int addr,
		unsigned int cmd, unsigned int *res);
		@@ -222,6 +308,200 @@ static inline void snd_hdac_codec_link_down(struct hdac_device *codec)
		clear_bit(codec->addr, &codec->bus->codec_powered);
		}

		int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val);
		int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
		unsigned int *res);

		bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset);
		void snd_hdac_bus_stop_chip(struct hdac_bus *bus);
		void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus);
		void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus);
		void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus);
		void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus);

		void snd_hdac_bus_update_rirb(struct hdac_bus *bus);
		void snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
		void (ack)(struct hdac_bus ,
		struct hdac_stream *));

		int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus);
		void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus);

		/*
		* macros for easy use
		*/
		#define _snd_hdac_chip_write(type, chip, reg, value) \
		((chip)->io_ops->reg_write ## type(value, (chip)->remap_addr + (reg)))
		#define _snd_hdac_chip_read(type, chip, reg) \
		((chip)->io_ops->reg_read ## type((chip)->remap_addr + (reg)))

		/* read/write a register, pass without AZX_REG_ prefix */
		#define snd_hdac_chip_writel(chip, reg, value) \
		_snd_hdac_chip_write(l, chip, AZX_REG_ ## reg, value)
		#define snd_hdac_chip_writew(chip, reg, value) \
		_snd_hdac_chip_write(w, chip, AZX_REG_ ## reg, value)
		#define snd_hdac_chip_writeb(chip, reg, value) \
		_snd_hdac_chip_write(b, chip, AZX_REG_ ## reg, value)
		#define snd_hdac_chip_readl(chip, reg) \
		_snd_hdac_chip_read(l, chip, AZX_REG_ ## reg)
		#define snd_hdac_chip_readw(chip, reg) \
		_snd_hdac_chip_read(w, chip, AZX_REG_ ## reg)
		#define snd_hdac_chip_readb(chip, reg) \
		_snd_hdac_chip_read(b, chip, AZX_REG_ ## reg)

		/* update a register, pass without AZX_REG_ prefix */
		#define snd_hdac_chip_updatel(chip, reg, mask, val) \
		snd_hdac_chip_writel(chip, reg, \
		(snd_hdac_chip_readl(chip, reg) & ~(mask)) \| (val))
		#define snd_hdac_chip_updatew(chip, reg, mask, val) \
		snd_hdac_chip_writew(chip, reg, \
		(snd_hdac_chip_readw(chip, reg) & ~(mask)) \| (val))
		#define snd_hdac_chip_updateb(chip, reg, mask, val) \
		snd_hdac_chip_writeb(chip, reg, \
		(snd_hdac_chip_readb(chip, reg) & ~(mask)) \| (val))

		/*
		* HD-audio stream
		*/
		struct hdac_stream {
		struct hdac_bus *bus;
		struct snd_dma_buffer bdl; /* BDL buffer */
		__le32 posbuf; / position buffer pointer */
		int direction; /* playback / capture (SNDRV_PCM_STREAM_) /

		unsigned int bufsize; /* size of the play buffer in bytes */
		unsigned int period_bytes; /* size of the period in bytes */
		unsigned int frags; /* number for period in the play buffer */
		unsigned int fifo_size; /* FIFO size */

		void __iomem sd_addr; / stream descriptor pointer */

		u32 sd_int_sta_mask; /* stream int status mask */

		/* pcm support */
		struct snd_pcm_substream substream; / assigned substream,
		* set in PCM open
		*/
		unsigned int format_val; /* format value to be set in the
		* controller and the codec
		*/
		unsigned char stream_tag; /* assigned stream */
		unsigned char index; /* stream index */
		int assigned_key; /* last device# key assigned to */

		bool opened:1;
		bool running:1;
		bool prepared:1;
		bool no_period_wakeup:1;
		bool locked:1;

		/* timestamp */
		unsigned long start_wallclk; /* start + minimum wallclk */
		unsigned long period_wallclk; /* wallclk for period */
		struct timecounter tc;
		struct cyclecounter cc;
		int delay_negative_threshold;

		struct list_head list;
		#ifdef CONFIG_SND_HDA_DSP_LOADER
		/* DSP access mutex */
		struct mutex dsp_mutex;
		#endif
		};

		void snd_hdac_stream_init(struct hdac_bus bus, struct hdac_stream azx_dev,
		int idx, int direction, int tag);
		struct hdac_stream snd_hdac_stream_assign(struct hdac_bus bus,
		struct snd_pcm_substream *substream);
		void snd_hdac_stream_release(struct hdac_stream *azx_dev);

		int snd_hdac_stream_setup(struct hdac_stream *azx_dev);
		void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev);
		int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev);
		int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
		unsigned int format_val);
		void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start);
		void snd_hdac_stream_clear(struct hdac_stream *azx_dev);
		void snd_hdac_stream_stop(struct hdac_stream *azx_dev);
		void snd_hdac_stream_reset(struct hdac_stream *azx_dev);
		void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
		unsigned int streams, unsigned int reg);
		void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
		unsigned int streams);
		void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
		unsigned int streams);
		/*
		* macros for easy use
		*/
		#define _snd_hdac_stream_write(type, dev, reg, value) \
		((dev)->bus->io_ops->reg_write ## type(value, (dev)->sd_addr + (reg)))
		#define _snd_hdac_stream_read(type, dev, reg) \
		((dev)->bus->io_ops->reg_read ## type((dev)->sd_addr + (reg)))

		/* read/write a register, pass without AZX_REG_ prefix */
		#define snd_hdac_stream_writel(dev, reg, value) \
		_snd_hdac_stream_write(l, dev, AZX_REG_ ## reg, value)
		#define snd_hdac_stream_writew(dev, reg, value) \
		_snd_hdac_stream_write(w, dev, AZX_REG_ ## reg, value)
		#define snd_hdac_stream_writeb(dev, reg, value) \
		_snd_hdac_stream_write(b, dev, AZX_REG_ ## reg, value)
		#define snd_hdac_stream_readl(dev, reg) \
		_snd_hdac_stream_read(l, dev, AZX_REG_ ## reg)
		#define snd_hdac_stream_readw(dev, reg) \
		_snd_hdac_stream_read(w, dev, AZX_REG_ ## reg)
		#define snd_hdac_stream_readb(dev, reg) \
		_snd_hdac_stream_read(b, dev, AZX_REG_ ## reg)

		/* update a register, pass without AZX_REG_ prefix */
		#define snd_hdac_stream_updatel(dev, reg, mask, val) \
		snd_hdac_stream_writel(dev, reg, \
		(snd_hdac_stream_readl(dev, reg) & \
		~(mask)) \| (val))
		#define snd_hdac_stream_updatew(dev, reg, mask, val) \
		snd_hdac_stream_writew(dev, reg, \
		(snd_hdac_stream_readw(dev, reg) & \
		~(mask)) \| (val))
		#define snd_hdac_stream_updateb(dev, reg, mask, val) \
		snd_hdac_stream_writeb(dev, reg, \
		(snd_hdac_stream_readb(dev, reg) & \
		~(mask)) \| (val))

		#ifdef CONFIG_SND_HDA_DSP_LOADER
		/* DSP lock helpers */
		#define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
		#define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
		#define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
		#define snd_hdac_stream_is_locked(dev) ((dev)->locked)
		/* DSP loader helpers */
		int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
		unsigned int byte_size, struct snd_dma_buffer *bufp);
		void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start);
		void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
		struct snd_dma_buffer *dmab);
		#else /* CONFIG_SND_HDA_DSP_LOADER */
		#define snd_hdac_dsp_lock_init(dev) do {} while (0)
		#define snd_hdac_dsp_lock(dev) do {} while (0)
		#define snd_hdac_dsp_unlock(dev) do {} while (0)
		#define snd_hdac_stream_is_locked(dev) 0

		static inline int
		snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
		unsigned int byte_size, struct snd_dma_buffer *bufp)
		{
		return 0;
		}

		static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
		{
		}

		static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
		struct snd_dma_buffer *dmab)
		{
		}
		#endif /* CONFIG_SND_HDA_DSP_LOADER */


		/*
		* generic array helpers
		*/

sound/hda/Kconfig

+3 −0

Original line number	Diff line number	Diff line
		config SND_HDA_CORE
		tristate
		select REGMAP

		config SND_HDA_DSP_LOADER
		bool

sound/hda/Makefile

+1 −1

Original line number	Diff line number	Diff line
		snd-hda-core-objs := hda_bus_type.o hdac_bus.o hdac_device.o hdac_sysfs.o \
		hdac_regmap.o array.o
		hdac_regmap.o hdac_controller.o hdac_stream.o array.o

		snd-hda-core-objs += trace.o
		CFLAGS_trace.o := -I$(src)

sound/hda/hdac_bus.c

+18 −2

Original line number	Diff line number	Diff line
		@@ -11,21 +11,36 @@

		static void process_unsol_events(struct work_struct *work);

		static const struct hdac_bus_ops default_ops = {
		.command = snd_hdac_bus_send_cmd,
		.get_response = snd_hdac_bus_get_response,
		};

		/**
		* snd_hdac_bus_init - initialize a HD-audio bas bus
		* @bus: the pointer to bus object
		* @ops: bus verb operators
		* @io_ops: lowlevel I/O operators
		*
		* Returns 0 if successful, or a negative error code.
		*/
		int snd_hdac_bus_init(struct hdac_bus bus, struct device dev,
		const struct hdac_bus_ops *ops)
		const struct hdac_bus_ops *ops,
		const struct hdac_io_ops *io_ops)
		{
		memset(bus, 0, sizeof(*bus));
		bus->dev = dev;
		if (ops)
		bus->ops = ops;
		else
		bus->ops = &default_ops;
		bus->io_ops = io_ops;
		INIT_LIST_HEAD(&bus->stream_list);
		INIT_LIST_HEAD(&bus->codec_list);
		INIT_WORK(&bus->unsol_work, process_unsol_events);
		spin_lock_init(&bus->reg_lock);
		mutex_init(&bus->cmd_mutex);
		bus->irq = -1;
		return 0;
		}
		EXPORT_SYMBOL_GPL(snd_hdac_bus_init);
		@@ -36,6 +51,7 @@ EXPORT_SYMBOL_GPL(snd_hdac_bus_init);
		*/
		void snd_hdac_bus_exit(struct hdac_bus *bus)
		{
		WARN_ON(!list_empty(&bus->stream_list));
		WARN_ON(!list_empty(&bus->codec_list));
		cancel_work_sync(&bus->unsol_work);
		}