Commit 8a86c3ae authored Jan 14, 2015 by Harini Katakam Committed by Wolfram Sang Jan 14, 2015

i2c: cadence: Check for errata condition involving master receive



Cadence I2C controller has the following bugs:
- completion indication is not given to the driver at the end of
a read/receive transfer with HOLD bit set.
- Invalid read transaction are generated on the bus when HW timeout
condition occurs with HOLD bit set.

As a result of the above, if a set of messages to be transferred with
repeated start includes any message following a read message,
completion is never indicated and timeout occurs.
Hence a check is implemented to return -EOPNOTSUPP for such sequences.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
Signed-off-by: Vishnu Motghare <vishnum@xilinx.com>
[wsa: fixed some whitespaces]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>

parent ef282914

drivers/i2c/busses/i2c-cadence.c

+14 −0

Original line number	Diff line number	Diff line
		@@ -545,6 +545,20 @@ static int cdns_i2c_master_xfer(struct i2c_adapter adap, struct i2c_msg msgs,
		* processed with a repeated start.
		*/
		if (num > 1) {
		/*
		* This controller does not give completion interrupt after a
		* master receive message if HOLD bit is set (repeated start),
		* resulting in SW timeout. Hence, if a receive message is
		* followed by any other message, an error is returned
		* indicating that this sequence is not supported.
		*/
		for (count = 0; count < num - 1; count++) {
		if (msgs[count].flags & I2C_M_RD) {
		dev_warn(adap->dev.parent,
		"Can't do repeated start after a receive message\n");
		return -EOPNOTSUPP;
		}
		}
		id->bus_hold_flag = 1;
		reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET);
		reg \|= CDNS_I2C_CR_HOLD;