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Commit 8a0559ed authored by Hareesh Gundu's avatar Hareesh Gundu
Browse files

msm: kgsl: Query xo resource addr from cmd-db driver 



Instead of hardcoding XO resource address in the PDC
initialization sequence, query it from cmd-db driver
to avoid conflict with other resources when it was
hard coded incorrectly.

Change-Id: Icbe903249345f82c8208ce066a22b55a957ee289
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
parent 93cda245

drivers/gpu/msm/adreno-gpulist.h

+0 −11
Original line number Diff line number Diff line
@@ -771,7 +771,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = { 
		.bus_width = 32,

	},

	.prim_fifo_threshold = 0x0018000,

	.pdc_address_offset = 0x00030080,

	.gmu_major = 1,

	.gmu_minor = 3,

	.sqefw_name = "a630_sqe.fw",
@@ -869,7 +868,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = { 
		.bus_width = 32,

	},

	.prim_fifo_threshold = 0x0018000,

	.pdc_address_offset = 0x00030080,

	.gmu_major = 1,

	.gmu_minor = 3,

	.sqefw_name = "a630_sqe.fw",
@@ -895,7 +893,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = { 
		.bus_width = 32,

	},

	.prim_fifo_threshold = 0x0018000,

	.pdc_address_offset = 0x00030090,

	.gmu_major = 1,

	.gmu_minor = 7,

	.sqefw_name = "a630_sqe.fw",
@@ -921,7 +918,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619 = { 
		.bus_width = 32,

	},

	.prim_fifo_threshold = 0x0018000,

	.pdc_address_offset = 0x000300a0,

	.gmu_major = 1,

	.gmu_minor = 9,

	.sqefw_name = "a630_sqe.fw",
@@ -1049,7 +1045,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = { 
		.bus_width = 32,

	},

	.prim_fifo_threshold = 0x0010000,

	.pdc_address_offset = 0x000300a0,

	.gmu_major = 2,

	.gmu_minor = 0,

	.sqefw_name = "a650_sqe.fw",
@@ -1138,7 +1133,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = { 
		.bus_width = 32,

	},

	.prim_fifo_threshold = 0x00200000,

	.pdc_address_offset = 0x00030090,

	.gmu_major = 2,

	.gmu_minor = 0,

	.sqefw_name = "a630_sqe.fw",
@@ -1217,7 +1211,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = { 
		.bus_width = 32,

	},

	.prim_fifo_threshold = 0x00300000,

	.pdc_address_offset = 0x000300A0,

	.gmu_major = 2,

	.gmu_minor = 0,

	.sqefw_name = "a650_sqe.fw",
@@ -1247,7 +1240,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = { 
		.bus_width = 32,

	},

	.prim_fifo_threshold = 0x00300000,

	.pdc_address_offset = 0x000300A0,

	.gmu_major = 2,

	.gmu_minor = 0,

	.sqefw_name = "a650_sqe.fw",
@@ -1274,7 +1266,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = { 
		.bus_width = 32,

	},

	.prim_fifo_threshold = 0x00400000,

	.pdc_address_offset = 0x00030090,

	.gmu_major = 2,

	.gmu_minor = 0,

	.sqefw_name = "a630_sqe.fw",
@@ -1350,7 +1341,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = { 
		.bus_width = 32,

	},

	.prim_fifo_threshold = 0x00080000,

	.pdc_address_offset = 0x00030080,

	.sqefw_name = "a630_sqe.fw",

	.gmufw_name = "a612_rgmu.bin",

	.zap_name = "a612_zap",
@@ -1374,7 +1364,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { 
		.bus_width = 32,

	},

	.prim_fifo_threshold = 0x0018000,

	.pdc_address_offset = 0x00030080,

	.gmu_major = 1,

	.gmu_minor = 3,

	.sqefw_name = "a630_sqe.fw",

drivers/gpu/msm/adreno_a6xx.h

+1 −3
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _ADRENO_A6XX_H_
@@ -42,8 +42,6 @@ struct adreno_a6xx_core { 
	u32 gmu_minor;

	/** @prim_fifo_threshold: target specific value for PC_DBG_ECO_CNTL */

	unsigned int prim_fifo_threshold;

	/** @pdc_address_offset: Offset for the PDC region for the target */

	unsigned int pdc_address_offset;

	/** @sqefw_name: Name of the SQE microcode file */

	const char *sqefw_name;

	/** @gmufw_name: Name of the GMU firmware file */

drivers/gpu/msm/adreno_a6xx_gmu.c

+9 −2
Original line number Diff line number Diff line
@@ -120,6 +120,13 @@ static int a6xx_load_pdc_ucode(struct kgsl_device *device) 
	void __iomem *cfg = NULL, *seq = NULL;

	const struct adreno_a6xx_core *a6xx_core = to_a6xx_core(adreno_dev);

	u32 vrm_resource_addr = cmd_db_read_addr("vrm.soc");

	u32 xo_resource_addr = cmd_db_read_addr("xo.lvl");



	if (!xo_resource_addr) {

		dev_err(&gmu->pdev->dev,

				"Failed to get 'xo.lvl' addr from cmd_db\n");

		return -ENOENT;

	}



	/*

	 * Older A6x platforms specified PDC registers in the DT using a
@@ -206,7 +213,7 @@ static int a6xx_load_pdc_ucode(struct kgsl_device *device) 
	_regwrite(cfg, PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);



	_regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2,

			a6xx_core->pdc_address_offset);

			xo_resource_addr);



	_regwrite(cfg, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x0);
@@ -237,7 +244,7 @@ static int a6xx_load_pdc_ucode(struct kgsl_device *device) 
	_regwrite(cfg, PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);



	_regwrite(cfg, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET * 2,

			a6xx_core->pdc_address_offset);

			xo_resource_addr);



	_regwrite(cfg, PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x3);