Merge branch 'irqdomain/next' of git://git.secretlab.ca/git/linux-2.6

irq_domain interrupt number mapping library

The current design of the Linux kernel uses a single large number

space where each separate IRQ source is assigned a different number.

This is simple when there is only one interrupt controller, but in

systems with multiple interrupt controllers the kernel must ensure

that each one gets assigned non-overlapping allocations of Linux

IRQ numbers.

The irq_alloc_desc*() and irq_free_desc*() APIs provide allocation of

irq numbers, but they don't provide any support for reverse mapping of

the controller-local IRQ (hwirq) number into the Linux IRQ number

space.

The irq_domain library adds mapping between hwirq and IRQ numbers on

top of the irq_alloc_desc*() API.  An irq_domain to manage mapping is

preferred over interrupt controller drivers open coding their own

reverse mapping scheme.

irq_domain also implements translation from Device Tree interrupt

specifiers to hwirq numbers, and can be easily extended to support

other IRQ topology data sources.

=== irq_domain usage ===

An interrupt controller driver creates and registers an irq_domain by

calling one of the irq_domain_add_*() functions (each mapping method

has a different allocator function, more on that later).  The function

will return a pointer to the irq_domain on success.  The caller must

provide the allocator function with an irq_domain_ops structure with

the .map callback populated as a minimum.

In most cases, the irq_domain will begin empty without any mappings

between hwirq and IRQ numbers.  Mappings are added to the irq_domain

by calling irq_create_mapping() which accepts the irq_domain and a

hwirq number as arguments.  If a mapping for the hwirq doesn't already

exist then it will allocate a new Linux irq_desc, associate it with

the hwirq, and call the .map() callback so the driver can perform any

required hardware setup.

When an interrupt is received, irq_find_mapping() function should

be used to find the Linux IRQ number from the hwirq number.

If the driver has the Linux IRQ number or the irq_data pointer, and

needs to know the associated hwirq number (such as in the irq_chip

callbacks) then it can be directly obtained from irq_data->hwirq.

=== Types of irq_domain mappings ===

There are several mechanisms available for reverse mapping from hwirq

to Linux irq, and each mechanism uses a different allocation function.

Which reverse map type should be used depends on the use case.  Each

of the reverse map types are described below:

==== Linear ====

irq_domain_add_linear()

The linear reverse map maintains a fixed size table indexed by the

hwirq number.  When a hwirq is mapped, an irq_desc is allocated for

the hwirq, and the IRQ number is stored in the table.

The Linear map is a good choice when the maximum number of hwirqs is

fixed and a relatively small number (~ < 256).  The advantages of this

map are fixed time lookup for IRQ numbers, and irq_descs are only

allocated for in-use IRQs.  The disadvantage is that the table must be

as large as the largest possible hwirq number.

The majority of drivers should use the linear map.

==== Tree ====

irq_domain_add_tree()

The irq_domain maintains a radix tree map from hwirq numbers to Linux

IRQs.  When an hwirq is mapped, an irq_desc is allocated and the

hwirq is used as the lookup key for the radix tree.

The tree map is a good choice if the hwirq number can be very large

since it doesn't need to allocate a table as large as the largest

hwirq number.  The disadvantage is that hwirq to IRQ number lookup is

dependent on how many entries are in the table.

Very few drivers should need this mapping.  At the moment, powerpc

iseries is the only user.

==== No Map ===-

irq_domain_add_nomap()

The No Map mapping is to be used when the hwirq number is

programmable in the hardware.  In this case it is best to program the

Linux IRQ number into the hardware itself so that no mapping is

required.  Calling irq_create_direct_mapping() will allocate a Linux

IRQ number and call the .map() callback so that driver can program the

Linux IRQ number into the hardware.

Most drivers cannot use this mapping.

==== Legacy ====

irq_domain_add_legacy()

irq_domain_add_legacy_isa()

The Legacy mapping is a special case for drivers that already have a

range of irq_descs allocated for the hwirqs.  It is used when the

driver cannot be immediately converted to use the linear mapping.  For

example, many embedded system board support files use a set of #defines

for IRQ numbers that are passed to struct device registrations.  In that

case the Linux IRQ numbers cannot be dynamically assigned and the legacy

mapping should be used.

The legacy map assumes a contiguous range of IRQ numbers has already

been allocated for the controller and that the IRQ number can be

calculated by adding a fixed offset to the hwirq number, and

visa-versa.  The disadvantage is that it requires the interrupt

controller to manage IRQ allocations and it requires an irq_desc to be

allocated for every hwirq, even if it is unused.

The legacy map should only be used if fixed IRQ mappings must be

supported.  For example, ISA controllers would use the legacy map for

mapping Linux IRQs 0-15 so that existing ISA drivers get the correct IRQ

numbers.

F:	net/ieee802154/

F:	drivers/ieee802154/

IIO SUBSYSTEM AND DRIVERS

M:	Jonathan Cameron <jic23@cam.ac.uk>

L:	linux-iio@vger.kernel.org

S:	Maintained

F:	drivers/staging/iio/

IKANOS/ADI EAGLE ADSL USB DRIVER

M:	Matthieu Castet <castet.matthieu@free.fr>

M:	Stanislaw Gruszka <stf_xl@wp.pl>

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core

F:	kernel/irq/

IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY)

M:	Benjamin Herrenschmidt <benh@kernel.crashing.org>

M:	Grant Likely <grant.likely@secretlab.ca>

T:	git git://git.secretlab.ca/git/linux-2.6.git irqdomain/next

S:	Maintained

F:	Documentation/IRQ-domain.txt

F:	include/linux/irqdomain.h

F:	kernel/irq/irqdomain.c

ISAPNP

M:	Jaroslav Kysela <perex@perex.cz>

S:	Maintained

};

struct gic_chip_data {

	unsigned int irq_offset;

	union gic_base dist_base;

	union gic_base cpu_base;

#ifdef CONFIG_CPU_PM

	u32 __percpu *saved_ppi_enable;

	u32 __percpu *saved_ppi_conf;

#endif

#ifdef CONFIG_IRQ_DOMAIN

	struct irq_domain domain;

#endif

	struct irq_domain *domain;

	unsigned int gic_irqs;

#ifdef CONFIG_GIC_NON_BANKED

	void __iomem *(*get_base)(union gic_base *);

		irqnr = irqstat & ~0x1c00;

		if (likely(irqnr > 15 && irqnr < 1021)) {

			irqnr = irq_domain_to_irq(&gic->domain, irqnr);

			irqnr = irq_find_mapping(gic->domain, irqnr);

			handle_IRQ(irqnr, regs);

			continue;

		}

	if (gic_irq == 1023)

		goto out;

	cascade_irq = irq_domain_to_irq(&chip_data->domain, gic_irq);

	if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))

	cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);

	if (unlikely(gic_irq < 32 || gic_irq > 1020))

		do_bad_IRQ(cascade_irq, desc);

	else

		generic_handle_irq(cascade_irq);

static void __init gic_dist_init(struct gic_chip_data *gic)

{

	unsigned int i, irq;

	unsigned int i;

	u32 cpumask;

	unsigned int gic_irqs = gic->gic_irqs;

	struct irq_domain *domain = &gic->domain;

	void __iomem *base = gic_data_dist_base(gic);

	u32 cpu = cpu_logical_map(smp_processor_id());

	for (i = 32; i < gic_irqs; i += 32)

		writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);

	/*

	 * Setup the Linux IRQ subsystem.

	 */

	irq_domain_for_each_irq(domain, i, irq) {

		if (i < 32) {

			irq_set_percpu_devid(irq);

			irq_set_chip_and_handler(irq, &gic_chip,

						 handle_percpu_devid_irq);

			set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);

		} else {

			irq_set_chip_and_handler(irq, &gic_chip,

						 handle_fasteoi_irq);

			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);

		}

		irq_set_chip_data(irq, gic);

	}

	writel_relaxed(1, base + GIC_DIST_CTRL);

}

}

#endif

#ifdef CONFIG_OF

static int gic_irq_domain_dt_translate(struct irq_domain *d,

static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,

				irq_hw_number_t hw)

{

	if (hw < 32) {

		irq_set_percpu_devid(irq);

		irq_set_chip_and_handler(irq, &gic_chip,

					 handle_percpu_devid_irq);

		set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);

	} else {

		irq_set_chip_and_handler(irq, &gic_chip,

					 handle_fasteoi_irq);

		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);

	}

	irq_set_chip_data(irq, d->host_data);

	return 0;

}

static int gic_irq_domain_xlate(struct irq_domain *d,

				struct device_node *controller,

				const u32 *intspec, unsigned int intsize,

				unsigned long *out_hwirq, unsigned int *out_type)

	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;

	return 0;

}

#endif

const struct irq_domain_ops gic_irq_domain_ops = {

#ifdef CONFIG_OF

	.dt_translate = gic_irq_domain_dt_translate,

#endif

	.map = gic_irq_domain_map,

	.xlate = gic_irq_domain_xlate,

};

void __init gic_init_bases(unsigned int gic_nr, int irq_start,

			   void __iomem *dist_base, void __iomem *cpu_base,

			   u32 percpu_offset)

			   u32 percpu_offset, struct device_node *node)

{

	irq_hw_number_t hwirq_base;

	struct gic_chip_data *gic;

	struct irq_domain *domain;

	int gic_irqs;

	int gic_irqs, irq_base;

	BUG_ON(gic_nr >= MAX_GIC_NR);

	gic = &gic_data[gic_nr];

	domain = &gic->domain;

#ifdef CONFIG_GIC_NON_BANKED

	if (percpu_offset) { /* Frankein-GIC without banked registers... */

		unsigned int cpu;

	 * For primary GICs, skip over SGIs.

	 * For secondary GICs, skip over PPIs, too.

	 */

	domain->hwirq_base = 32;

	hwirq_base = 32;

	if (gic_nr == 0) {

		if ((irq_start & 31) > 0) {

			domain->hwirq_base = 16;

			hwirq_base = 16;

			if (irq_start != -1)

				irq_start = (irq_start & ~31) + 16;

		}

		gic_irqs = 1020;

	gic->gic_irqs = gic_irqs;

	domain->nr_irq = gic_irqs - domain->hwirq_base;

	domain->irq_base = irq_alloc_descs(irq_start, 16, domain->nr_irq,

					   numa_node_id());

	if (IS_ERR_VALUE(domain->irq_base)) {

	gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */

	irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());

	if (IS_ERR_VALUE(irq_base)) {

		WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",

		     irq_start);

		domain->irq_base = irq_start;

		irq_base = irq_start;

	}

	domain->priv = gic;

	domain->ops = &gic_irq_domain_ops;

	irq_domain_add(domain);

	gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,

				    hwirq_base, &gic_irq_domain_ops, gic);

	if (WARN_ON(!gic->domain))

		return;

	gic_chip.flags |= gic_arch_extn.flags;

	gic_dist_init(gic);

	void __iomem *dist_base;

	u32 percpu_offset;

	int irq;

	struct irq_domain *domain = &gic_data[gic_cnt].domain;

	if (WARN_ON(!node))

		return -ENODEV;

	if (of_property_read_u32(node, "cpu-offset", &percpu_offset))

		percpu_offset = 0;

	domain->of_node = of_node_get(node);

	gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset);

	gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);

	if (parent) {

		irq = irq_of_parse_and_map(node, 0);

	u32		int_enable;

	u32		soft_int;

	u32		protect;

	struct irq_domain domain;

	struct irq_domain *domain;

};

/* we cannot allocate memory when VICs are initially registered */

	v->resume_sources = resume_sources;

	v->irq = irq;

	vic_id++;

	v->domain.irq_base = irq;

	v->domain.nr_irq = 32;

#ifdef CONFIG_OF_IRQ

	v->domain.of_node = of_node_get(node);

#endif /* CONFIG_OF */

	v->domain.ops = &irq_domain_simple_ops;

	irq_domain_add(&v->domain);

	v->domain = irq_domain_add_legacy(node, 32, irq, 0,

					  &irq_domain_simple_ops, v);

}

static void vic_ack_irq(struct irq_data *d)

	vic_register(base, irq_start, 0, node);

}

static void __init __vic_init(void __iomem *base, unsigned int irq_start,

void __init __vic_init(void __iomem *base, unsigned int irq_start,

			      u32 vic_sources, u32 resume_sources,

			      struct device_node *node)

{

	stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);

	while (stat) {

		irq = ffs(stat) - 1;

		handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);

		handle_IRQ(irq_find_mapping(vic->domain, irq), regs);

		stat &= ~(1 << irq);

		handled = 1;

	}

extern struct irq_chip gic_arch_extn;

void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,

		    u32 offset);

		    u32 offset, struct device_node *);

int gic_of_init(struct device_node *node, struct device_node *parent);

void gic_secondary_init(unsigned int);

void gic_handle_irq(struct pt_regs *regs);

static inline void gic_init(unsigned int nr, int start,

			    void __iomem *dist , void __iomem *cpu)

{

	gic_init_bases(nr, start, dist, cpu, 0);

	gic_init_bases(nr, start, dist, cpu, 0, NULL);

}

#endif