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Commit 89c4a306 authored by Mark Rutland's avatar Mark Rutland Committed by Catalin Marinas
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arm64: add MIDR_EL1 field accessors 



The MIDR_EL1 register is composed of a number of bitfields, and uses of
the fields has so far involved open-coding of the shifts and masks
required.

This patch adds shifts and masks for each of the MIDR_EL1 subfields, and
also provides accessors built atop of these. Existing uses within
cputype.h are updated to use these accessors.

The read_cpuid_part_number macro is modified to return the extracted
bitfield rather than returning the value in-place with all other fields
(including revision) masked out, to better match the other accessors.
As the value is only used in comparison with the *_CPU_PART_* macros
which are similarly updated, and these values are never exposed to
userspace, this change should not affect any functionality.

Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 18ab7db6

arch/arm64/include/asm/cputype.h

+26 −7
Original line number Diff line number Diff line
@@ -38,15 +38,34 @@ 
	__val;								\

})



#define MIDR_REVISION_MASK	0xf

#define MIDR_REVISION(midr)	((midr) & MIDR_REVISION_MASK)

#define MIDR_PARTNUM_SHIFT	4

#define MIDR_PARTNUM_MASK	(0xfff << MIDR_PARTNUM_SHIFT)

#define MIDR_PARTNUM(midr)	\

	(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)

#define MIDR_ARCHITECTURE_SHIFT	16

#define MIDR_ARCHITECTURE_MASK	(0xf << MIDR_ARCHITECTURE_SHIFT)

#define MIDR_ARCHITECTURE(midr)	\

	(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)

#define MIDR_VARIANT_SHIFT	20

#define MIDR_VARIANT_MASK	(0xf << MIDR_VARIANT_SHIFT)

#define MIDR_VARIANT(midr)	\

	(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)

#define MIDR_IMPLEMENTOR_SHIFT	24

#define MIDR_IMPLEMENTOR_MASK	(0xff << MIDR_IMPLEMENTOR_SHIFT)

#define MIDR_IMPLEMENTOR(midr)	\

	(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)



#define ARM_CPU_IMP_ARM		0x41

#define ARM_CPU_IMP_APM		0x50



#define ARM_CPU_PART_AEM_V8	0xD0F0

#define ARM_CPU_PART_FOUNDATION	0xD000

#define ARM_CPU_PART_CORTEX_A53	0xD030

#define ARM_CPU_PART_CORTEX_A57	0xD070

#define ARM_CPU_PART_AEM_V8	0xD0F

#define ARM_CPU_PART_FOUNDATION	0xD00

#define ARM_CPU_PART_CORTEX_A57	0xD07

#define ARM_CPU_PART_CORTEX_A53	0xD03



#define APM_CPU_PART_POTENZA	0x0000

#define APM_CPU_PART_POTENZA	0x000



#ifndef __ASSEMBLY__
@@ -67,12 +86,12 @@ static inline u64 __attribute_const__ read_cpuid_mpidr(void) 


static inline unsigned int __attribute_const__ read_cpuid_implementor(void)

{

	return (read_cpuid_id() & 0xFF000000) >> 24;

	return MIDR_IMPLEMENTOR(read_cpuid_id());

}



static inline unsigned int __attribute_const__ read_cpuid_part_number(void)

{

	return (read_cpuid_id() & 0xFFF0);

	return MIDR_PARTNUM(read_cpuid_id());

}



static inline u32 __attribute_const__ read_cpuid_cachetype(void)