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Commit 894b7382 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'irq-s3c24xx-for-v3.10' of... 

Merge tag 'irq-s3c24xx-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

From Kukjin Kim <kgene.kim@samsung.com>:

s3c24xx irq cleanup and move into drivers/irqchip

* tag 'irq-s3c24xx-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung

:
  irqchip: s3c24xx: add devicetree support
  irqchip: s3c24xx: make interrupt handling independent of irq_domain structure
  irqchip: s3c24xx: globally keep track of the created intc instances
  irqchip: s3c24xx: add irq_set_type callback for basic interrupt types
  irqchip: s3c24xx: fix irqlist of second s3c2416 controller
  irqchip: s3c24xx: fix comments on some camera interrupts
  ARM: S3C24XX: move irq driver to drivers/irqchip
  ARM: S3C24XX: add handle_irq function
  ARM: S3C24XX: make s3c24xx_init_intc static
  ARM: S3C24XX: move s3c24xx_init_irq to s3c2410_init_irq
  ARM: S3C24XX: fix irq parent check
  ARM: S3C24XX: fix redundant checks in the irq mapping function

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents ab9838e1 f0774d41

Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt

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Samsung S3C24XX Interrupt Controllers



The S3C24XX SoCs contain a custom set of interrupt controllers providing a

varying number of interrupt sources. The set consists of a main- and sub-

controller and on newer SoCs even a second main controller.



Required properties:

- compatible: Compatible property value should be "samsung,s3c2410-irq"

  for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.



- reg: Physical base address of the controller and length of memory mapped

  region.



- interrupt-controller : Identifies the node as an interrupt controller



- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value shall be 4 and interrupt descriptor shall

  have the following format:

      <ctrl_num parent_irq ctrl_irq type>



  ctrl_num contains the controller to use:

      - 0 ... main controller

      - 1 ... sub controller

      - 2 ... second main controller on s3c2416 and s3c2450

  parent_irq contains the parent bit in the main controller and will be

             ignored in main controllers

  ctrl_irq contains the interrupt bit of the controller

  type contains the trigger type to use



Example:



	interrupt-controller@4a000000 {

		compatible = "samsung,s3c2410-irq";

		reg = <0x4a000000 0x100>;

		interrupt-controller;

		#interrupt-cells=<4>;

	};



	[...]



	serial@50000000 {

		compatible = "samsung,s3c2410-uart";

		reg = <0x50000000 0x4000>;

		interrupt-parent = <&subintc>;

		interrupts = <1 28 0 4>, <1 28 1 4>;

	};



	rtc@57000000 {

		compatible = "samsung,s3c2410-rtc";

		reg = <0x57000000 0x100>;

		interrupt-parent = <&intc>;

		interrupts = <0 30 0 3>, <0 8 0 3>;

	};

arch/arm/Kconfig

+1 −0
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@@ -778,6 +778,7 @@ config ARCH_S3C24XX 
	select HAVE_S3C2410_I2C if I2C

	select HAVE_S3C2410_WATCHDOG if WATCHDOG

	select HAVE_S3C_RTC if RTC_CLASS

	select MULTI_IRQ_HANDLER

	select NEED_MACH_GPIO_H

	select NEED_MACH_IO_H

	help

arch/arm/mach-s3c24xx/Makefile

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@@ -14,7 +14,7 @@ obj- := 


# core



obj-y				+= common.o irq.o

obj-y				+= common.o



obj-$(CONFIG_CPU_S3C2410)	+= s3c2410.o

obj-$(CONFIG_S3C2410_CPUFREQ)	+= cpufreq-s3c2410.o

arch/arm/mach-s3c24xx/common.h

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@@ -21,6 +21,7 @@ extern void s3c2410_map_io(void); 
extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);

extern void s3c2410_init_clocks(int xtal);

extern void s3c2410_restart(char mode, const char *cmd);

extern void s3c2410_init_irq(void);

#else

#define s3c2410_init_clocks NULL

#define s3c2410_init_uarts NULL

arch/arm/mach-s3c24xx/include/mach/entry-macro.S

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+0 −70
Original line number Diff line number Diff line 
/*

 * arch/arm/mach-s3c2410/include/mach/entry-macro.S

 *

 * Low-level IRQ helper macros for S3C2410-based platforms

 *

 * This file is licensed under  the terms of the GNU General Public

 * License version 2. This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

*/



/* We have a problem that the INTOFFSET register does not always

 * show one interrupt. Occasionally we get two interrupts through

 * the prioritiser, and this causes the INTOFFSET register to show

 * what looks like the logical-or of the two interrupt numbers.

 *

 * Thanks to Klaus, Shannon, et al for helping to debug this problem

*/



#define INTPND		(0x10)

#define INTOFFSET	(0x14)



#include <mach/hardware.h>

#include <asm/irq.h>



	.macro  get_irqnr_preamble, base, tmp

	.endm



	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp



		mov	\base, #S3C24XX_VA_IRQ



		@@ try the interrupt offset register, since it is there



		ldr	\irqstat, [\base, #INTPND ]

		teq	\irqstat, #0

		beq	1002f

		ldr	\irqnr, [\base, #INTOFFSET ]

		mov	\tmp, #1

		tst	\irqstat, \tmp, lsl \irqnr

		bne	1001f



		@@ the number specified is not a valid irq, so try

		@@ and work it out for ourselves



		mov	\irqnr, #0		@@ start here



		@@ work out which irq (if any) we got



		movs	\tmp, \irqstat, lsl#16

		addeq	\irqnr, \irqnr, #16

		moveq	\irqstat, \irqstat, lsr#16

		tst	\irqstat, #0xff

		addeq	\irqnr, \irqnr, #8

		moveq	\irqstat, \irqstat, lsr#8

		tst	\irqstat, #0xf

		addeq	\irqnr, \irqnr, #4

		moveq	\irqstat, \irqstat, lsr#4

		tst	\irqstat, #0x3

		addeq	\irqnr, \irqnr, #2

		moveq	\irqstat, \irqstat, lsr#2

		tst	\irqstat, #0x1

		addeq	\irqnr, \irqnr, #1



		@@ we have the value

1001:

		adds	\irqnr, \irqnr, #IRQ_EINT0

1002:

		@@ exit here, Z flag unset if IRQ



	.endm