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Commit 89301471 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: update generated headers 



Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 41e69778

drivers/gpu/drm/msm/adreno/a2xx.xml.h

+50 −8
Original line number Diff line number Diff line
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git 
The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32814 bytes, from 2013-11-30 15:07:33)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   8900 bytes, from 2013-10-22 23:57:49)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  10574 bytes, from 2013-11-13 05:44:45)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  53644 bytes, from 2013-11-30 15:07:33)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (   8344 bytes, from 2013-11-30 14:49:47)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-25 12:57:16)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-25 12:57:16)



Copyright (C) 2013 by the following authors:

Copyright (C) 2013-2014 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)



Permission is hereby granted, free of charge, to any person obtaining
@@ -203,6 +203,15 @@ enum a2xx_rb_copy_sample_select { 
	SAMPLE_0123 = 6,

};



enum a2xx_rb_blend_opcode {

	BLEND_DST_PLUS_SRC = 0,

	BLEND_SRC_MINUS_DST = 1,

	BLEND_MIN_DST_SRC = 2,

	BLEND_MAX_DST_SRC = 3,

	BLEND_DST_MINUS_SRC = 4,

	BLEND_DST_PLUS_SRC_BIAS = 5,

};



enum adreno_mmu_clnt_beh {

	BEH_NEVR = 0,

	BEH_TRAN_RNG = 1,
@@ -890,6 +899,39 @@ static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 
#define REG_A2XX_VGT_EVENT_INITIATOR				0x000021f9



#define REG_A2XX_VGT_DRAW_INITIATOR				0x000021fc

#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK			0x0000003f

#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT		0

static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)

{

	return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;

}

#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK		0x000000c0

#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT		6

static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)

{

	return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;

}

#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK			0x00000600

#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT			9

static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)

{

	return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;

}

#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK		0x00000800

#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT		11

static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)

{

	return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;

}

#define A2XX_VGT_DRAW_INITIATOR_NOT_EOP				0x00001000

#define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX			0x00002000

#define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE	0x00004000

#define A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK		0xffff0000

#define A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT		16

static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INDICES(uint32_t val)

{

	return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK;

}



#define REG_A2XX_VGT_IMMED_DATA					0x000021fd
@@ -963,7 +1005,7 @@ static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend 
}

#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK		0x000000e0

#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT		5

static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum adreno_rb_blend_opcode val)

static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)

{

	return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;

}
@@ -981,7 +1023,7 @@ static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend 
}

#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK		0x00e00000

#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT		21

static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum adreno_rb_blend_opcode val)

static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)

{

	return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;

}

drivers/gpu/drm/msm/adreno/a3xx.xml.h

+245 −51

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/msm/adreno/a3xx_gpu.h

+5 −0
Original line number Diff line number Diff line
@@ -19,6 +19,11 @@ 
#define __A3XX_GPU_H__



#include "adreno_gpu.h"



/* arrg, somehow fb.h is getting pulled in: */

#undef ROP_COPY

#undef ROP_XOR



#include "a3xx.xml.h"



struct a3xx_gpu {

drivers/gpu/drm/msm/adreno/adreno_common.xml.h

+41 −15
Original line number Diff line number Diff line
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git 
The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32814 bytes, from 2013-11-30 15:07:33)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   8900 bytes, from 2013-10-22 23:57:49)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  10574 bytes, from 2013-11-13 05:44:45)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  53644 bytes, from 2013-11-30 15:07:33)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (   8344 bytes, from 2013-11-30 14:49:47)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-25 12:57:16)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-25 12:57:16)



Copyright (C) 2013 by the following authors:

Copyright (C) 2013-2014 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)



Permission is hereby granted, free of charge, to any person obtaining
@@ -87,15 +87,6 @@ enum adreno_rb_blend_factor { 
	FACTOR_SRC_ALPHA_SATURATE = 16,

};



enum adreno_rb_blend_opcode {

	BLEND_DST_PLUS_SRC = 0,

	BLEND_SRC_MINUS_DST = 1,

	BLEND_MIN_DST_SRC = 2,

	BLEND_MAX_DST_SRC = 3,

	BLEND_DST_MINUS_SRC = 4,

	BLEND_DST_PLUS_SRC_BIAS = 5,

};



enum adreno_rb_surface_endian {

	ENDIAN_NONE = 0,

	ENDIAN_8IN16 = 1,
@@ -116,6 +107,39 @@ enum adreno_rb_depth_format { 
	DEPTHX_24_8 = 1,

};



enum adreno_rb_copy_control_mode {

	RB_COPY_RESOLVE = 1,

	RB_COPY_CLEAR = 2,

	RB_COPY_DEPTH_STENCIL = 5,

};



enum a3xx_render_mode {

	RB_RENDERING_PASS = 0,

	RB_TILING_PASS = 1,

	RB_RESOLVE_PASS = 2,

	RB_COMPUTE_PASS = 3,

};



enum a3xx_msaa_samples {

	MSAA_ONE = 0,

	MSAA_TWO = 1,

	MSAA_FOUR = 2,

};



enum a3xx_threadmode {

	MULTI = 0,

	SINGLE = 1,

};



enum a3xx_instrbuffermode {

	BUFFER = 1,

};



enum a3xx_threadsize {

	TWO_QUADS = 0,

	FOUR_QUADS = 1,

};



#define REG_AXXX_CP_RB_BASE					0x000001c0



#define REG_AXXX_CP_RB_CNTL					0x000001c1
@@ -264,6 +288,8 @@ static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) 
#define REG_AXXX_CP_INT_ACK					0x000001f4



#define REG_AXXX_CP_ME_CNTL					0x000001f6

#define AXXX_CP_ME_CNTL_BUSY					0x20000000

#define AXXX_CP_ME_CNTL_HALT					0x10000000



#define REG_AXXX_CP_ME_STATUS					0x000001f7

drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h

+233 −6
Original line number Diff line number Diff line
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git 
The rules-ng-ng source files this header was generated from are:

- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)

- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32814 bytes, from 2013-11-30 15:07:33)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   8900 bytes, from 2013-10-22 23:57:49)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  10574 bytes, from 2013-11-13 05:44:45)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  53644 bytes, from 2013-11-30 15:07:33)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (   8344 bytes, from 2013-11-30 14:49:47)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14477 bytes, from 2014-05-16 11:51:57)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  58020 bytes, from 2014-06-25 12:57:16)

- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  26602 bytes, from 2014-06-25 12:57:16)



Copyright (C) 2013 by the following authors:

Copyright (C) 2013-2014 by the following authors:

- Rob Clark <robdclark@gmail.com> (robclark)



Permission is hereby granted, free of charge, to any person obtaining
@@ -105,6 +105,7 @@ enum pc_di_index_size { 


enum pc_di_vis_cull_mode {

	IGNORE_VISIBILITY = 0,

	USE_VISIBILITY = 1,

};



enum adreno_pm4_packet_type {
@@ -163,6 +164,11 @@ enum adreno_pm4_type3_packets { 
	CP_SET_BIN = 76,

	CP_TEST_TWO_MEMS = 113,

	CP_WAIT_FOR_ME = 19,

	CP_SET_DRAW_STATE = 67,

	CP_DRAW_INDX_OFFSET = 56,

	CP_DRAW_INDIRECT = 40,

	CP_DRAW_INDX_INDIRECT = 41,

	CP_DRAW_AUTO = 36,

	IN_IB_PREFETCH_END = 23,

	IN_SUBBLK_PREFETCH = 31,

	IN_INSTR_PREFETCH = 32,
@@ -232,6 +238,211 @@ static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) 
	return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;

}



#define REG_CP_DRAW_INDX_0					0x00000000

#define CP_DRAW_INDX_0_VIZ_QUERY__MASK				0xffffffff

#define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT				0

static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)

{

	return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;

}



#define REG_CP_DRAW_INDX_1					0x00000001

#define CP_DRAW_INDX_1_PRIM_TYPE__MASK				0x0000003f

#define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT				0

static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)

{

	return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;

}

#define CP_DRAW_INDX_1_SOURCE_SELECT__MASK			0x000000c0

#define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT			6

static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)

{

	return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;

}

#define CP_DRAW_INDX_1_VIS_CULL__MASK				0x00000600

#define CP_DRAW_INDX_1_VIS_CULL__SHIFT				9

static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)

{

	return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;

}

#define CP_DRAW_INDX_1_INDEX_SIZE__MASK				0x00000800

#define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT			11

static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)

{

	return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;

}

#define CP_DRAW_INDX_1_NOT_EOP					0x00001000

#define CP_DRAW_INDX_1_SMALL_INDEX				0x00002000

#define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE		0x00004000

#define CP_DRAW_INDX_1_NUM_INDICES__MASK			0xffff0000

#define CP_DRAW_INDX_1_NUM_INDICES__SHIFT			16

static inline uint32_t CP_DRAW_INDX_1_NUM_INDICES(uint32_t val)

{

	return ((val) << CP_DRAW_INDX_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_1_NUM_INDICES__MASK;

}



#define REG_CP_DRAW_INDX_2					0x00000002

#define CP_DRAW_INDX_2_NUM_INDICES__MASK			0xffffffff

#define CP_DRAW_INDX_2_NUM_INDICES__SHIFT			0

static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)

{

	return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;

}



#define REG_CP_DRAW_INDX_2					0x00000002

#define CP_DRAW_INDX_2_INDX_BASE__MASK				0xffffffff

#define CP_DRAW_INDX_2_INDX_BASE__SHIFT				0

static inline uint32_t CP_DRAW_INDX_2_INDX_BASE(uint32_t val)

{

	return ((val) << CP_DRAW_INDX_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_2_INDX_BASE__MASK;

}



#define REG_CP_DRAW_INDX_2					0x00000002

#define CP_DRAW_INDX_2_INDX_SIZE__MASK				0xffffffff

#define CP_DRAW_INDX_2_INDX_SIZE__SHIFT				0

static inline uint32_t CP_DRAW_INDX_2_INDX_SIZE(uint32_t val)

{

	return ((val) << CP_DRAW_INDX_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_2_INDX_SIZE__MASK;

}



#define REG_CP_DRAW_INDX_2_0					0x00000000

#define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK			0xffffffff

#define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT			0

static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)

{

	return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;

}



#define REG_CP_DRAW_INDX_2_1					0x00000001

#define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK			0x0000003f

#define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT			0

static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)

{

	return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;

}

#define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK			0x000000c0

#define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT			6

static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)

{

	return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;

}

#define CP_DRAW_INDX_2_1_VIS_CULL__MASK				0x00000600

#define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT			9

static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)

{

	return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;

}

#define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK			0x00000800

#define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT			11

static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)

{

	return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;

}

#define CP_DRAW_INDX_2_1_NOT_EOP				0x00001000

#define CP_DRAW_INDX_2_1_SMALL_INDEX				0x00002000

#define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE		0x00004000

#define CP_DRAW_INDX_2_1_NUM_INDICES__MASK			0xffff0000

#define CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT			16

static inline uint32_t CP_DRAW_INDX_2_1_NUM_INDICES(uint32_t val)

{

	return ((val) << CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INDICES__MASK;

}



#define REG_CP_DRAW_INDX_2_2					0x00000002

#define CP_DRAW_INDX_2_2_NUM_INDICES__MASK			0xffffffff

#define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT			0

static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)

{

	return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;

}



#define REG_CP_DRAW_INDX_OFFSET_0				0x00000000

#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK			0x0000003f

#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT			0

static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)

{

	return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;

}

#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK		0x000000c0

#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT		6

static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)

{

	return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;

}

#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK			0x00000700

#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT			8

static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)

{

	return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;

}

#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK			0x00000800

#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT			11

static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum pc_di_index_size val)

{

	return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;

}

#define CP_DRAW_INDX_OFFSET_0_NOT_EOP				0x00001000

#define CP_DRAW_INDX_OFFSET_0_SMALL_INDEX			0x00002000

#define CP_DRAW_INDX_OFFSET_0_PRE_DRAW_INITIATOR_ENABLE		0x00004000

#define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK			0xffff0000

#define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT		16

static inline uint32_t CP_DRAW_INDX_OFFSET_0_NUM_INDICES(uint32_t val)

{

	return ((val) << CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK;

}



#define REG_CP_DRAW_INDX_OFFSET_1				0x00000001



#define REG_CP_DRAW_INDX_OFFSET_2				0x00000002

#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK			0xffffffff

#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT		0

static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)

{

	return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;

}



#define REG_CP_DRAW_INDX_OFFSET_2				0x00000002

#define CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK			0xffffffff

#define CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT			0

static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_BASE(uint32_t val)

{

	return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK;

}



#define REG_CP_DRAW_INDX_OFFSET_2				0x00000002

#define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK			0xffffffff

#define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT			0

static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_SIZE(uint32_t val)

{

	return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK;

}



#define REG_CP_SET_DRAW_STATE_0					0x00000000

#define CP_SET_DRAW_STATE_0_COUNT__MASK				0x0000ffff

#define CP_SET_DRAW_STATE_0_COUNT__SHIFT			0

static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val)

{

	return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK;

}

#define CP_SET_DRAW_STATE_0_DIRTY				0x00010000

#define CP_SET_DRAW_STATE_0_DISABLE				0x00020000

#define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS			0x00040000

#define CP_SET_DRAW_STATE_0_LOAD_IMMED				0x00080000

#define CP_SET_DRAW_STATE_0_GROUP_ID__MASK			0x1f000000

#define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT			24

static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val)

{

	return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK;

}



#define REG_CP_SET_DRAW_STATE_1					0x00000001

#define CP_SET_DRAW_STATE_1_ADDR__MASK				0xffffffff

#define CP_SET_DRAW_STATE_1_ADDR__SHIFT				0

static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val)

{

	return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK;

}



#define REG_CP_SET_BIN_0					0x00000000



#define REG_CP_SET_BIN_1					0x00000001
@@ -262,5 +473,21 @@ static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) 
	return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;

}



#define REG_CP_SET_BIN_DATA_0					0x00000000

#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK			0xffffffff

#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT			0

static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)

{

	return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;

}



#define REG_CP_SET_BIN_DATA_1					0x00000001

#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK		0xffffffff

#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT		0

static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)

{

	return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;

}





#endif /* ADRENO_PM4_XML */