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Commit 8904976e authored by John A. Williams's avatar John A. Williams Committed by Michal Simek
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microblaze: Unprivileged stream instruction awareness 



Add cpuinfo support for the new MicroBlaze option permitting userspace
(unprivileged) access to the streaming instructions (FSL / AXI-stream).

Emit a noisy warning at bootup if this is enabled, because bad user code
can potentially lockup the CPU.

Signed-off-by: default avatarJohn A. Williams <john.williams@petalogix.com>
Signed-off-by: default avatarMichal Simek <monstr@monstr.eu>
parent 5db34eb9

arch/microblaze/include/asm/cpuinfo.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -38,6 +38,7 @@ struct cpuinfo { 
	u32 use_exc;

	u32 use_exc;

	u32 ver_code;

	u32 ver_code;

	u32 mmu;

	u32 mmu;

	u32 mmu_privins;

	u32 endian;

	u32 endian;





	/* CPU caches */

	/* CPU caches */

arch/microblaze/include/asm/pvr.h

+2 −1
Original line number Original line Diff line number Diff line
@@ -117,10 +117,10 @@ struct pvr_s { 
#define PVR11_MMU_DTLB_SIZE		0x07000000

#define PVR11_MMU_DTLB_SIZE		0x07000000

#define PVR11_MMU_TLB_ACCESS		0x00C00000

#define PVR11_MMU_TLB_ACCESS		0x00C00000

#define PVR11_MMU_ZONES			0x003C0000

#define PVR11_MMU_ZONES			0x003C0000

#define PVR11_MMU_PRIVINS		0x00010000

/* MSR Reset value PVR mask */

/* MSR Reset value PVR mask */

#define PVR11_MSR_RESET_VALUE_MASK	0x000007FF

#define PVR11_MSR_RESET_VALUE_MASK	0x000007FF







/* PVR access macros */

/* PVR access macros */

#define PVR_IS_FULL(_pvr)	(_pvr.pvr[0] & PVR0_PVR_FULL_MASK)

#define PVR_IS_FULL(_pvr)	(_pvr.pvr[0] & PVR0_PVR_FULL_MASK)

#define PVR_USE_BARREL(_pvr)	(_pvr.pvr[0] & PVR0_USE_BARREL_MASK)

#define PVR_USE_BARREL(_pvr)	(_pvr.pvr[0] & PVR0_USE_BARREL_MASK)
@@ -216,6 +216,7 @@ struct pvr_s { 
#define PVR_MMU_DTLB_SIZE(_pvr)		(_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)

#define PVR_MMU_DTLB_SIZE(_pvr)		(_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)

#define PVR_MMU_TLB_ACCESS(_pvr)	(_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)

#define PVR_MMU_TLB_ACCESS(_pvr)	(_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)

#define PVR_MMU_ZONES(_pvr)		(_pvr.pvr[11] & PVR11_MMU_ZONES)

#define PVR_MMU_ZONES(_pvr)		(_pvr.pvr[11] & PVR11_MMU_ZONES)

#define PVR_MMU_PRIVINS(pvr)		(pvr.pvr[11] & PVR11_MMU_PRIVINS)





/* endian */

/* endian */

#define PVR_ENDIAN(_pvr)	(_pvr.pvr[0] & PVR0_ENDI)

#define PVR_ENDIAN(_pvr)	(_pvr.pvr[0] & PVR0_ENDI)

arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -72,6 +72,7 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu) 
	CI(pvr_user2, USER2);

	CI(pvr_user2, USER2);





	CI(mmu, USE_MMU);

	CI(mmu, USE_MMU);

	CI(mmu_privins, MMU_PRIVINS);

	CI(endian, ENDIAN);

	CI(endian, ENDIAN);





	CI(use_icache, USE_ICACHE);

	CI(use_icache, USE_ICACHE);

arch/microblaze/kernel/cpu/cpuinfo-static.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -119,6 +119,7 @@ void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu) 
	ci->pvr_user2 = fcpu(cpu, "xlnx,pvr-user2");

	ci->pvr_user2 = fcpu(cpu, "xlnx,pvr-user2");





	ci->mmu = fcpu(cpu, "xlnx,use-mmu");

	ci->mmu = fcpu(cpu, "xlnx,use-mmu");

	ci->mmu_privins = fcpu(cpu, "xlnx,mmu-privileged-instr");

	ci->endian = fcpu(cpu, "xlnx,endianness");

	ci->endian = fcpu(cpu, "xlnx,endianness");





	ci->ver_code = 0;

	ci->ver_code = 0;

arch/microblaze/kernel/cpu/cpuinfo.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -88,4 +88,8 @@ void __init setup_cpuinfo(void) 
		printk(KERN_WARNING "%s: Unsupported PVR setting\n", __func__);

		printk(KERN_WARNING "%s: Unsupported PVR setting\n", __func__);

		set_cpuinfo_static(&cpuinfo, cpu);

		set_cpuinfo_static(&cpuinfo, cpu);

	}

	}



	if (cpuinfo.mmu_privins)

		printk(KERN_WARNING "%s: Stream instructions enabled"

			" - USERSPACE CAN LOCK THIS KERNEL!\n", __func__);

}
 
}