Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 89000e89 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/host-layerscape' into next 

* pci/host-layerscape:
  PCI: layerscape: Change default error response behavior
  PCI: Disable MSI for Freescale Layerscape PCIe RC mode
  arm64: dts: ls1046a: Add PCIe controller DT nodes
  arm64: dts: ls1012a: Add PCIe controller DT node
  PCI: layerscape: Add support for ls1012a
  arm64: dts: ls1012a: Add MSI controller DT node
  irqchip/ls-scfg-msi: Add LS1012a MSI support
parents aaea12f7 84d897d6

Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ Required properties: 
              "fsl,ls1043a-msi"

              "fsl,ls1046a-msi"

              "fsl,ls1043a-v1.1-msi"

              "fsl,ls1012a-msi"

- msi-controller: indicates that this is a PCIe MSI controller node

- reg: physical base address of the controller and length of memory mapped.

- interrupts: an interrupt to the parent interrupt controller.

Documentation/devicetree/bindings/pci/layerscape-pci.txt

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ Required properties: 
        "fsl,ls2088a-pcie"

        "fsl,ls1088a-pcie"

        "fsl,ls1046a-pcie"

        "fsl,ls1012a-pcie"

- reg: base addresses and lengths of the PCIe controller register blocks.

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

+31 −0
Original line number Diff line number Diff line
@@ -471,5 +471,36 @@ 
			dr_mode = "host";

			phy_type = "ulpi";

		};



		msi: msi-controller1@1572000 {

			compatible = "fsl,ls1012a-msi";

			reg = <0x0 0x1572000 0x0 0x8>;

			msi-controller;

			interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;

		};



		pcie@3400000 {

			compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";

			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */

			reg-names = "regs", "config";

			interrupts = <0 118 0x4>, /* controller interrupt */

				     <0 117 0x4>; /* PME interrupt */

			interrupt-names = "aer", "pme";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			num-lanes = <4>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */

				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

			msi-parent = <&msi>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;

		};

	};

};

arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

+75 −0
Original line number Diff line number Diff line
@@ -661,6 +661,81 @@ 
				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;

		};



		pcie@3400000 {

			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";

			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */

			reg-names = "regs", "config";

			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */

			interrupt-names = "aer", "pme";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			dma-coherent;

			num-lanes = <4>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */

				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

			msi-parent = <&msi1>, <&msi2>, <&msi3>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;

		};



		pcie@3500000 {

			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";

			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */

			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */

			reg-names = "regs", "config";

			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */

				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */

			interrupt-names = "aer", "pme";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			dma-coherent;

			num-lanes = <2>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */

				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

			msi-parent = <&msi2>, <&msi3>, <&msi1>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

		};



		pcie@3600000 {

			compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";

			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */

			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */

			reg-names = "regs", "config";

			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */

				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */

			interrupt-names = "aer", "pme";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			dma-coherent;

			num-lanes = <2>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */

				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

			msi-parent = <&msi3>, <&msi1>, <&msi2>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,

					<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;

		};



	};



	reserved-memory {

drivers/irqchip/irq-ls-scfg-msi.c

+1 −0
Original line number Diff line number Diff line
@@ -316,6 +316,7 @@ static const struct of_device_id ls_scfg_msi_id[] = { 
	{ .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg},

	{ .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg},



	{ .compatible = "fsl,ls1012a-msi", .data = &ls1021_msi_cfg },

	{ .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },

	{ .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },

	{ .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },